Shelendra Kumar

Bengaluru

Summary

Experienced Senior Design Engineer with skills in checking logical designs, ensuring multiple voltage rules, and using a unified power format. I'm good at using TCL programming language and know industry standards. I've made significant contributions to projects, leading to improvements in efficiency and effectiveness. I'm dedicated to advancing design engineering and encouraging innovation in the field.

Overview

years of professional experience

Work History

Senior Design Engineer

Infineon Technologies

Bangalore

07.2022 - Current

ASIC Design Verification.

Executed Multi-Voltage Rule Check and Logic Equivalence Check throughout different phases of the ASIC flow, guaranteeing design reliability.
Utilized Unified Power Format (UPF) and IEEE Standard 1801 to manage power intent and voltage-aware design.

Education

Master of Engineering - Microelectronics

Birla Institute of Technology And Science, Pilani

Pilani

07-2022

Bachelor of Technology - Electronics And Communications Engineering

Madan Mohan Malaviya University of Technology

Gorakhpur

08-2019

Intermediate

GKIC Khair, Aligarh

Khair,Aligarh

05-2013

Skills

I have worked in ASIC design flow (RTL to GDS)
Excellent understanding and hands-on experience in sign-off domains, LEC, and CLP

Comfortable in scripting language (TCL)

Tool Experiences: Synopsys Formality, MVRC tool, Cadence Conformal (LEC/CLP)

CAREER OBJECTIVE

Senior Design Engineer with expertise in LEC/CLP and Conformal Tools, seeking to expand skills in Static Timing Analysis (STA) to drive innovation and optimize high-performance semiconductor designs.

AREA OF INTEREST

Static Timing Analysis (STA),Place & Route (PNR),Synthesis & Optimization,Logic Equivalence Checking (LEC),Multivoltage Rule Check (MVRC)

Timeline