SHIBANA N

400G Flow Processor using Versal HBM

• The basic function of the design is to support 400 Gbps datapath via Versal FPGA and to support up to 200 Gbps datapath via QDMA CPM5 PCIe with the help of a DPDK application.

The FPGA Datapath is responsible for various data processing tasks:

● Packet Parsing: Incoming packets are processed by the FPGA pipelines, including tasks like header parsing, protocol identification, and payload extraction.

● Redirection: Based on predefined rules, packets can be redirected to different destinations within the FPGA or external systems. This allows for efficient load balancing and traffic distribution.

● Modification: The FPGA pipelines can modify packet headers, contents, or other attributes as per the configured rules. This can involve tasks like encapsulation, decapsulation, and payload manipulation.

FPGA based Video protocol Converter

• The design converts LVDS input, parallel camera input to MIPI CSI-2 format
• FPGA performs reception and packing of the Frame data received through LVDS channels/parallel lines and transmitting the frame data as MIPI CSI-2 format
• Implementation of RTL modules for decoding the embedded sync & pixel data information from the stream
• Testing and verification of design on board

Development of custom MIPI Transmitter IP

• Design and implementation of video MIPI Interface with YUV 420 and 422 format
• Testing, Validation of the design for MIPI output signals(MIPI 4 lane Transmitter) and board bring-up
• Development of custom MIPI Transmitter IP core which can accept three input video streams and support configurable virtual channel ID and resolution as per MIPI standard

Offloading of Open Virtual Switch functions

• Design and Implementation of the FPGA logic for offloading ENC/DEC algorithm
• Testing and validation of the design U25N board