Shivam Kumar
Physical Design Engineer (Graduate)
Chennai,TN
Summary
M.Tech VLSI graduate with foundational experience in backend VLSI design, including Physical Design and Static Timing Analysis. Familiar with RTL-to-GDSII flow, timing closure concepts, and EDA tools used in PD/STA environments. Seeking a backend VLSI role to contribute to silicon implementation and timing optimization.
Overview
2
2
years of professional experience
Work History
RTL to GDS Flow for Washing Machine
01.2024 - 05.2024
- Designed RTL architecture of a washing machine controller with modules like control logic, timer, and userinterface using Verilog, followed by functional verification and coverage analysis through simulations
- Performed synthesis, formal equivalence checking, DFT, and STA to optimize area, timing, and functionality
- Executed full physical design flow, including floorplanning, placement, CTS, and routing to generate manufacturable GDSII
Impact of Testability on PPAS
01.2024 - 06.2025
- Developed a comprehensive PPAS (Power, Performance, Area, Sustainability) evaluation framework to assess the sustainability impact of various testability techniques in VLSI design
- Implemented scan insertion on synthesized designs with conventional scan and compression methods.
- Generated ATPG (Automatic Test Pattern Generation) for all methods, achieving a high fault coverage of 99.60%, and validated test effectiveness
RISC-V IP Physical Design
07.2025 - 10.2025
- Created and optimized two hard macros for RISC-V sub-modules using Design Compiler, ensuring PPA
- Successfully integrated these macros into the top-level design through floorplanning, placement, and routing in ICC2
- Achieved timing closure while meeting stringent power constraints with STA in PrimeTime
AOI321 Domino Logic Gate Design
08.2023 - 11.2023
- Designed and laid out an AOI321 complex logic gate in Cadence Virtuoso (65nm PDK, 13T standard cell height), achieving minimal area with DRC/LVS-clean results
- Conducted pre- and post-layout PPA (performance, power, area) analysis across multiple PVT corners to verify timingrobustness and functionality
Education
M.Tech - Electronics & Communication Engineering (VLSI)
Indraprastha Institute of Information Technology
Delhi07.2025
B.Tech - Electronics & Communication Engineering
Bengal College of Engineering & Technology
Durgapur09.2021
Skills
HDL & Programming: Verilog
EDA Tools: Cadence Virtuoso, Calibre, Synopsys Design Compiler, PrimeTime STA, Fusion Compiler, ModelSim,Innovus, Genus, Tempus
Physical design, Digital VLSI Design(DVD), RTL-to-GDSII flow, Static timing analysis (STA), Place-and-Route, Floorplanning
Accomplishments
- Served as Head Teaching Assistant for Convex Optimization at IIIT-Delhi, managing 200+ students and coordinating a team of TAs
- Teaching Assistant for courses in Digital Circuits and Basic Electronics
- Qualified GATE 2023 (AIR 2528) and GATE 2022 (AIR 4422) in Electronics & Communication Engineering
- First Runner-Up in B.Tech inter-college tech quiz “Adhyayan”, showcasing competitive technical knowledge
Interests
Cricket — Runner-up, “Karwaan” Cricket Tournament, IIIT-Delhi
Timeline
RISC-V IP Physical Design
07.2025 - 10.2025
RTL to GDS Flow for Washing Machine
01.2024 - 05.2024
Impact of Testability on PPAS
01.2024 - 06.2025
AOI321 Domino Logic Gate Design
08.2023 - 11.2023
B.Tech - Electronics & Communication Engineering
Bengal College of Engineering & Technology
M.Tech - Electronics & Communication Engineering (VLSI)
Indraprastha Institute of Information Technology