Shivam Kumar
Synopsys India
Noida
2
years of professional experience
Senior Standard cell/Layout Design Engineer with 2 years of experience in advanced-node (2nm–4nm) standard cell and layout design. Proven expertise in PPA optimization, EM/IR robustness, and automation-driven productivity improvements across Intel, Samsung, and Rapidus technologies
Work History
Sr. Standard Cell Layout Design Engineer
2 Years- Developed Layouts in cutting edge latest tech nodes like Samsung 2nm/4nm Rapidus 2nm, Global Foundries 55nm BCD, Intel 18A, 14AE (with back side power delivery network).
- Designed and optimized Libraries at 2nm-4nm, addressing EUV-driven DRC, pin accessibility, EM/IR, and achieving delay improvement area saving using Synopsys custom compiler tool, IC compiler tool, ICV tool , ICC2 and mentor calibre for signoff checks (DRC, LVS, DFM, ERC).
- Reviewed signoff for 70%-80% of cells, providing quality feedback on area and metal reduction for 5-10% of cells, enhancing overall design integrity.
- Worked on IPDEV library development and release activities , including job/environment setup and handling large data (gds , lvs , lef , spx and other views) .
- Applied advanced-node layout methodologies to mitigate Electromigration (EM), antenna, IR-drop, cross talk, ESD, Layout Parasitic and abutment issues in dense libraries, ensuring first-pass signoff at 3nm/2nm.
- Have hand's on experience with ICV coding , DRC rule deck development and updation to perform PDK /impact analysis .
- Experience on unix environment, flow debugging, scripting for automation (python, bash, Shell).
- Understanding of analog layout , matching techniques also familiar with layout dependent effects , parasitics and impact on circuit performance.
Education
Master of Engineering - Microelectronics
B.Tech - Electrical Engineering
Skills
Tools: Synopsys Custom Compiler
Synopsys IC Compiler (ICC2)
ICV
Mentor Calibre
Cadence Virtuoso (exposure).
ICV coding exposure to maintain DRC decks during PDK refresh.
Computer software/frameworks: Office applications
MATLAB
Excel.
Programming languages: Python
Verilog
TCL
Bash/Shell.
Timeline
Sr. Standard Cell Layout Design Engineer
Synopsys India
09.2024 - CurrentRead More
Birla Institute of Technology And Science, Pilani
Master of Engineering from Microelectronics
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JSS Academy of Technical Education Noida
B.Tech from Electrical Engineering
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