Priyanka Umrani
Gadag
Summary
Senior Analog Layout Engineer with 8.5+ years of experience in PMIC, ADC, LDO, and Mixed-Signal SoC design across TSMC, GlobalFoundries, VIS, and TI technologies. Expertise in full-chip layout, advanced matching techniques, reliability sign-off, and tape-out execution from 180nm to 28nm nodes. Proven leader with a strong record of delivering complex semiconductor products on schedule while mentoring teams and driving technical excellence.
Overview
8
8
years of professional experience
Work History
Senior Member of Technical Staff
Smartsoc Solutions Pvt Ltd.
Hubli
05.2022 - Current
- Delivered TSMC 90nm ECG chip single-handedly, meeting all project constraints within 7 months
- Led a team of 5 members completing 2 simultaneous projects in GF 180nm BCD and TSMC 180nm BCD
- Executed all reliability tests - EM, Antenna, MetalFill, Floating Metal, Density, IR at chip level; resolved critical PEX issues, enabling timely project release
- Debugged critical contact and parasitic issues during server migration, ensuring successful completion of 2 versions of Power Management full chips in GF 180nm BCD
- Worked on high-voltage VIS 150nm BCD technology (1.2 years)
Analog Layout Engineer
Texas Instruments India
Bangalore
09.2018 - 04.2022
- Developed a wide range of layouts including amplifiers, bias circuits, digital blocks, and PGA_TOP across 65nm, 28nm, and 130nm, contributing to project versatility and success (1.2 years)
- Highly matched comparators - Precision SAR ADC, SC network from floorplan to verification including all reliability checks (1 year)
- Critical clock blocks: RING_OSC, IO_I2C, RCCR_TO_CMOS and sub-blocks in 28nm across 3 projects (8 months)
- Designed layout for daisy chain across two complete chips - 28nm and 130nm, ensuring design integrity and manufacturability (4 months)
- LDOs up to 120mA, CAP_RSTBUF_CH_SET, LDO TOP Backend in 130nm and 28nm (8 months)
- RESP_INA TOP, Lead Detect AC TOP, RESP_TX_CH_TOP in 130nm (4 months)
- Mentored juniors in SAR ADC project for clock blocks; delivered on time
- Worked on test structures for new PDK development (HPA9 - internal to TI)
- Honoured with 'Best Employee of the Year' and 'Executive Excellence' awards for commitment to quality and timely delivery across two major projects.
Analog Layout Design Engineer (Training)
Sankalp Semiconductor Pvt Ltd.
Hubli
01.2018 - 09.2018
Education
Bachelor of Engineering - Electronics & Communication
KLE Dr. M.S. Sheshgiri College of Engg & Tech
Belagavi01-2017
Intermediate (PUC Science) -
Bipin Chikkatti PU Science College
Gadag01-2013
Schooling (SSLC) -
Lions English Medium School
Gadag, Karnataka01-2011
Skills
- GPDK 180nm & 45nm
- TI 65nm
- TSMC 28nm & 90nm
- VIS 150nm
- GF 180nm BCD
- Matching & Shielding
- WPE and LOD effects
- Floorplan & Placement
- Area Estimation
- Full Chip Physical Verification
- Verification & Reliability
- DRC
- DFM
- ERC
- LVS
- Antenna Effect & Latch-up
- Electromigration (EM)
- Back Annotation (Assura & PVS)
- Density Errors & IR Analysis
- Cadence Virtuoso L & XL
- MOSFETs & Daisy Chain
- Fabrication Process
- PEX & Parasitic Analysis
- Custom Analog Block Design
Accomplishments
- 1st Prize, 5th International Level Science Talent Examination, 2003
- 1st Rank, Karnataka Talent Search Examination, Gadag Center, 2008
- 1st Prize, CHANAKYA-2013 District Level PU College Quiz Competition, 2013
- Best Speaker Award, Eklakshya Training Competitions, 2018
- Published Article, "Monitor Electricity Through WiFi" in CircuitDigest Magazine with Texas Instruments, 2019
- Excellent Contribution Recognition, Project Sukshma, 2021 (Critical Cap Parasitic Blocks), 2021
Languages
Kannada (Mother Tongue)
English
Hindi
Custom Section
- Served as Student Secretary and active IEEE member
- Led teams with strong organizational skills at Sankalp Semiconductors during training
- Volunteered for Back to School, Quiz, and Nutrition Garden initiatives under Texas Instruments' global program
- Attended SNUG 25 (2025-07-10) - gained knowledge on new semiconductor fields
- Quick to adapt to change and cope with diverse situations
- Managed and mentored junior engineers across multiple projects
Awards
- Best Employee of the Year
- Executive Excellence award for hard work and on-time delivery across 2 different projects
Disclaimer
I, Priyanka Umrani, hereby confirm that all information provided is true to the best of my knowledge and I hold myself responsible if any irregularities are found.
Timeline
Senior Member of Technical Staff
Smartsoc Solutions Pvt Ltd.
05.2022 - Current
Analog Layout Engineer
Texas Instruments India
09.2018 - 04.2022
Analog Layout Design Engineer (Training)
Sankalp Semiconductor Pvt Ltd.
01.2018 - 09.2018
Bachelor of Engineering - Electronics & Communication
KLE Dr. M.S. Sheshgiri College of Engg & Tech
Intermediate (PUC Science) -
Bipin Chikkatti PU Science College
Schooling (SSLC) -
Lions English Medium School