Shivani Sharma

• Responsible for RTL to GDS implementation for CPU partition as well as interconnect low power Fabric blocks
• Targeted maximum frequency of operation with acceptable power and area numbers – best PPA tradeoff
• Teamed up with architecture & RTL folks on minimizing power numbers for power hungry modules
• Expertise in placement (congestion resolution) and CTS
• Multiple preventives like module padding, partial density screen, ispatial, cloning , increasing NDR for EGR, uniform density, high congestion effort, staggered blockage, HEOC used for design convergence
• Recognized with an award for my contribution to designing and implementing Google’s 1st generation 4.5Ghz FLL design
• Driving constraints development across blocks, expertise in constraints development from scratch
• Awarded spot/peer bonus several times within a duration of 4 years

• Responsible for executing SOC level Synthesis, Constraints development (functional/atpg modes),LEC & STA for multi clock domain design(upto 1.8GHz at 45nm )
• Awarded with Silver recognition at TI for flawless execution on timing closure for one of the timing critical blocks
• Responsible for Netlist to GDSII handoff for two subchips
• Expertise in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, along with a background in implementing them through ECOs.
• Understanding of DFT logic ( scan shift and capture modes ) and hands-on experience in design closure.
• Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.
• Knowledge in process variation effect modeling and experience in design convergence taking into account variations.
• Experience in critical path planning and crafting.

Design and implementation of Delay Detection and measurement technique using Razor flop in digital circuits.