Summary
Education
Skills
Websites
Accomplishments
Languages
Examinations
Projects
Disclaimer
Timeline
Generic

Shivkanya Rajgure

Pune

Summary

Organized and dependable candidate successful at managing multiple priorities with a positive attitude. Hardworking and passionate job seeker with strong organizational skills eager to secure entry-level position. Ready to help the team achieve company goals.

Education

Electronics And Communications Engineering

PCCOE,Pune
05.2024

SSC

Jnana Prabodhini Navanagar Vidyalaya
Nigdi, Pune
05.2018

Skills

  • Object-oriented programming
  • Data structure and algorithm
  • DBMS
  • Verilog, SV, VHDL, UVM
  • OS:- Windows, Linux
  • Digital Design, Analog Design
  • Basic Protocols UART, SPI, I2C, AMBA APB
  • Friendly, Positive Attitude
  • Teamwork and Collaboration
  • Customer Service
  • Problem-Solving
  • Time Management

Accomplishments

  • Lila Girl 2020 from Lila Poonawalla foundation(LPF)-get selected
  • Research Journal publication-"Synchronization of Smart Irrigation with Minimal Wastage of Water"
  • Corporate Readiness Program - Atlas Copco India Ltd.

Languages

English
Hindi
Marathi

Examinations

  • PCCOE, 2020-2024, Graduation, 8.19
  • Shri Mahalsakant Junior College, 2018-2020, 12th, 85%
  • Jnana Prabodhini Navanagar Vidyalaya, 2018, 10th, 88.8%

Projects

  • Underground Water level measurement sensor for borewells, Generate a sine wave using DAC of esp8266, amplify the sine wave transmit wave through the transmitter, received by mic unit, calculating the distance. Design using component, flash memory, Arduino uno, output on OLED or serial monitor, maximum depth output is 300 foot, software used for audacity software.
  • Design of a pattern detector, Pattern detector on serial input coming to design implement using Moore FSM and mealy. FSM, notice change in number of states. It requires coding an FSM to detect each pattern till it reaches to final pattern. Implemented test bench randomly generates series of 0 and 1s to check the pattern.
  • Router 1x3 design pocket based Protocol, This router design contains three output ports and three input ports, it is packet based Protocol. This Design consists Registers and FIFO. For larger networks, where a direct-mapped approach is not feasible due to FPGA resource limitations, a virtualized time-multiplexed approach was used. Synchronization between router FSM and router FIFO modules is provided by this module. It ensures that the one input port and three output ports are in constant communication.

Disclaimer

I hereby declare that all the information contained in this resume is facts or truths to my sense. I take full authority for the correctness of the written information.

Timeline

Electronics And Communications Engineering

PCCOE,Pune

SSC

Jnana Prabodhini Navanagar Vidyalaya
Shivkanya Rajgure