SHRADDHA KUMARI

Aspiring software developer and electronics engineer with robust technical skills and a commitment to tackling new challenges. Demonstrates strong work ethic, adaptability, and exceptional interpersonal skills, enabling effective collaboration within diverse teams.

Side Channel Attack and Resistance Using Countermeasures on AES

• Developed AES encryption in Verilog using Vivado, and extracted power reports in CSV format to perform a Side Channel Attack (SCA) using Python, successfully recovering the secret key
• Implemented masking countermeasures in AES, which prevented key retrieval during SCA, demonstrating effective resistance against the attack

Implementation of the AES algorithm on software and FPGA

• In the project, we have used software: Xilinx ISE 14.7, and hardware HDL: Verilog. In this project, we implemented the 128-bit key-based AES for 128-bit data
• The proposed 128-bit AES algorithm is highly optimized in key schedule and sub-bytes blocks for area and power

Simple Electronic Voting System using Verilog HDL Counters

• This project presents a simple Electronic Voting System using a minimalist approach, utilizing Verilog Hardware Description Language (HDL) for instructional purposes
• Implement the voting system by integrating various Verilog components to create functional counter mechanisms

• Digital electronics (Coursera)
• Infosys Springboard Introduction to Cybersecurity
• Emerging technologies (AI and Cloud)
• Hardware Description Languages for FPGA Design (Coursera)
• Embedded System and IOT