SHRADDHA KUUMARI

Responsible and motivated student ready to apply education in the workplace. Offers excellent technical abilities with software and applications, ability to handle challenging work, and excellent time management skills. Desire to take on new challenges. Strong work ethic, adaptability, and exceptional interpersonal skills.

• Singing
• Reading Fiction Novel
• Dancing
• Engaging in Art and Craft

• Embedded System Using IoT
• Digital Electronics (Coursera)
• Introduction to Cybersecurity (Infosys Springboard)
• Emerging Technologies (AI and Cloud)
• Hardware Description Languages for FPGA Design (Coursera)

• First Place in Regional Singing Competition, Recognized with first place honors in a regional singing competition, showcasing musical talent.
• Participation Award in Quiz Competitions, Engaged in multiple quiz competitions, demonstrating knowledge across various subjects.
• Selected in Supar100 Exam, Successfully selected in the competitive Supar100 exam, highlighting academic excellence.
• Training Program Participation, Participated in a comprehensive training program focusing on integrated horticultural practices.

Side Channel Attack and Resistance using countermeasures on AES -Current

• Analyze power consumption and timing information to understand vulnerabilities in AES encryption during side channel attacks.
• Develop and configure the FPGA Board hardware to effectively execute side channel attacks on AES implementations.
• Implement countermeasures, such as masking techniques, to enhance the resilience of AES against side channel attack vectors.
  

AES Encryption on Software and FPGA

• Developed the AES encryption algorithm in software using Xilinx 14.7, focusing on achieving reliable and secure data protection.
• Implemented the AES algorithm on an FPGA platform using Verilog HDL,allowing for enhanced performance and parallel processing capabilities.
• Optimized execution time of the AES algorithm on FPGA, resulting in faster encryption and decryption processes for real-time applications

Simple Electronic Voting System using Verilog HDL Counters

• Design a minimalist electronic voting system using Verilog HDL to facilitate understanding of digital design concepts.
• Develop counter logic circuits that accurately tabulate votes, focusing on efficiency and clarity for educational purposes.
• Implement the voting system by integrating various Verilog components to create functional counter mechanisms.