Shreyas Muniyappa

• Part of 3 successfully taped-out project from Habana Intel
• PnR activities - RTL2GDS i.e., Synthesis, Floorplan, PnR, Formality, DRC/LVS fixes, Timing closure (PT) & RHSC, complete block signoff, Methodology development, Flow development
• Products: Falcon shore 1, Gaudi 3, Gaudi 2 & smarti9
• Handled Blocks: PCIe blocks (PMMU/PIF), NIC blocks (TX), NOC(Channel block), Media Blocks(TBH, parc_nort_south channel block)
• Technology: 5nm, 7nm, 16nm
• Frequency: 1.6GHz, 800MHz
• Cell count: 800k till 3M
• Flow: Inway, Makefile, Cheetah
• Responsibilities undertaken at Intel:

- Multi-Source custom CTS, Ports placement, macro placement according to data-flowline and PG checks, DRC checks before placement, constraints, SDC writing & bound creation

- Timing & GR analysis at placement stage and feedback to RTL team on the quality metrics such as MB ratio/ICG %, ungated flops etc

MSCTS QC & QoR checks

- Connectivity, crosstalk, shorts checks & fixes at PnR

- Formality checks and feedback to the designer for any missing connection

- Complete block signoff in all aspects such as DRVs, DRC/LVS, Timing closure, other Sign-off checks

- As part of methodology written GTL checker script which captures some of the important metrics from the netlist and tabulates in table format, written in python-tcl interface

- Functional eco implementation and formality checks

- Library benchmarking and PPA analysis, i.e., N7 TSMC vs N5 SNPS, N7 TSMC vs N6 TSMC, N5p SNPS vs N5p TSMC, TSMC N3 vs N5

• Client: Broadcom
• Project 1: (WCC Group)
• Technology: 28nm
• Role: Block owner of 5 blocks
• Block Details: [Block-1, Block-2, Block-3, Block-4, Block-5]
• Instance count: 150k
• HM count: 32
• Responsibility: [PnR, VCLP, LEC, STA, PV]

- Macro placement, ESD cell, power switch and power mux connections

- Placement analysis and GR congestion analysis and reduction techniques

- CTS QoR checks

- Connectivity checks at route stage

- VCLP checks and fixes

- LEC checks and fixes

- STA analysis

- DRC, LVS, ERC and ANT analysis and fixes

• Part of three successfully taped-out projects in Qualcomm
• Technology: 14nm, 10nm
• Role and Responsibilities: Responsible as a person of contact (POC) for the Libgen of the project undertaken
• Written PERL scripts to ease the manual work in the LibGen flow
• Generated multiple input views required for the Physical design PnR process
• QA checks made for the all the input views generated
• Issues faced while generating input models and NDMs: Standard cell doesn’t reference a defined SITE, Standard cell with inconsistent SITE height, GDS pin usage (signal/power/ground) differs from LEF, Cell mismatch across different corners in libs, Signal pin in .lib doesn’t specify related power/ground pin, LEF cell missing in LIB, Milkyway has no FRAM views