Optimization of Critical Path in Digital VLSI Circuit Using Logical Effort Model (Oct 2024 – Dec 2024, ECED, IITR)
• Analyzed RTL design to optimize the critical path in a digital circuit.
• Used Synopsys PrimeTime for critical path extraction and Logical Effort model for gate sizing.
• Designed and implemented optimized schematic in Cadence Virtuoso, ensuring compliance with design constraints.
• Conducted post-layout verification (DRC, LVS, timing analysis), achieving improved efficiency.
Design a Standard cell Library for Low Power CMOS Circuits (Mar 2025 – May 2025, ECED, IITR)
• Studied IEEE research papers to identify methodologies for optimizing standard cells for low-power CMOS design.
• Designed a 28nm standard cell library using Cadence Virtuoso and Synopsys HSPICE, focusing on energy efficiency.
• Built a complete custom design flow covering Verilog, schematic, layout, and post-layout extraction.
• Characterized cells through HSPICE timing analysis, showing that the proposed cells are more efficient at low Vdd compared to conventional cells at higher Vdd.
Design and Analysis of Two-Stage CMOS Op-Amp Using 180nm Technology (Sep 2024 – Nov 2024, ECED, IITR)
• Designed a two-stage CMOS operational amplifier in Cadence Virtuoso.
• Implemented Miller compensation for stability and improved frequency response.
• Conducted DC, AC, and transient simulations to evaluate gain, bandwidth, and phase margin.
RISC-V Processor Implementation using Verilog and Logisim (Feb 2025 – May 2025, ECED, IITR)
• Designed a basic non-pipelined RISC-V processor architecture to understand instruction set execution flow.
• Performed block-level simulation in Logisim to validate individual modules and overall functionality.
• Implemented processor blocks in Verilog, verified them through simulation, and integrated the complete RV32I design in Vivado to ensure correct execution of instructions (excluding ecall and ebreak).
