Shreyas Yewale

Integrated Dual Degree (B.Tech + M.Tech) student in Electrical and Electronics Engineering at IIT Roorkee with expertise in Microelectronics and VLSI. Passionate about semiconductor and chip technologies. Skilled in circuit design, analysis, and optimization using industry-standard tools. Strong teamwork and problem-solving abilities.

• Achieved an All India Rank of 5004 in the Joint Entrance Examination Advanced 2021.
• Received the HOD's Appreciation Award in 2024 & 2025 for best performance in academics.

Optimization of Critical Path in Digital VLSI Circuit Using Logical Effort (Oct–Dec 2024, IIT Roorkee)

• Identified and optimized critical path in an RTL design using Synopsys PrimeTime.
• Applied Logical Effort–based gate sizing and implemented optimized schematic in Cadence Virtuoso.
• Completed post-layout checks (DRC/LVS/timing), achieving improved delay efficiency.

Low-Power Standard Cell Library Design (Mar–May 2025, IIT Roorkee)

• Designed energy-efficient 28 nm CMOS standard cells using Virtuoso and HSPICE.
• Built complete custom design flow (Verilog → schematic → layout → extraction → characterization).
• HSPICE timing analysis showed improved efficiency at low Vdd compared to conventional cells.

Two-Stage CMOS Op-Amp Design (Sep–Nov 2024, IIT Roorkee)

• Designed a two-stage op-amp with Miller compensation in Virtuoso.
• Performed DC/AC/transient simulations to analyze gain, bandwidth, and phase margin.

RISC-V Processor Implementation (Feb–May 2025, IIT Roorkee)

• Designed a non-pipelined RV32I processor using Verilog & Logisim.
• Verified modules through simulation and integrated design in Vivado (excluding ecall/ebreak).