Shruti Jain

• 128Kx8 bit low power CMOS static random access memory  (Prof.Kaushik Saha, IIT Delhi): (January,2022 - April,2022) 

- Implemented SRAM cell array, Write Driver circuit, ATD pulse width generator, Row decoder, Column multiplexer and  Sense amplifier 

- Simulations and layouts were implemented using Cadence Virtuoso and Layout Suite using 65nm technology 

• Characterization of FFT using learnt ML model (Prof.Jayadeva, IIT Delhi): (January,2022 - April,2022)

 - Synthesized FFT Verilog codes on Cadence Genus and performed PVT variations

 - Used ML models to determine the critical path over the PVT space 

• Standard Cell Design in UMC65nm Technology (Prof. Jayadeva and Kaushik Saha, IIT Delhi): (August,2021 - December,2021)

 - Designed schematics and layouts of Standard Cells using Cadence Virtuoso and Layout Suite 

- Verified DRC, LVS, PEX and Post-layout simulation 

• Two Stage Single Ended Operational Amplifier (Prof.Rakesh Kumar Palani, IIT Delhi): (August,2021 - December,2021) 

- Supply 1.5V, low power and high gain OPAMPS designed using Cadence Virtuoso 

- Specifications: DC Gain 62.4dB, UGB 150MHz, PM 60 deg 

• 8×8 Wallace Tree Multiplier circuit (Prof.Basabi Bhaumik, IIT Delhi): (August,2021 - December,2021) 

- Schematic of 8×8 multiplier using high order compressor circuits (3:2, 4:2, 5:2) was designed using Cadence Virtuoso 

- Supply 1.2V, Power Dissipated 200nW, Delay 80ns 

• RTL to GDSII fow of asynchronous FIFO (Professor - Jayadeva and Kaushik Saha, IIT Delhi): (March,2022 - April,2022) 

- Synthesized asynchronous FIFO on Cadence Genus 

- Performed Floor Planning, Placement, Routing and Timing analysis on Cadence Innovus tool