SHUBHAM CHOUHAN
Delhi
Summary
Electrical Engineer and M.Tech Gold Medalist specializing in Quantum Communication and FPGA-based system design, with strong expertise in Quantum Key Distribution (QKD), QKD post-processing, and the design of Digital Control, RF, and Analog Electronics for high-performance quantum and optical communication systems.
Overview
1
1
year of professional experience
Work History
Project Scientist
Optics and Photonics Centre IIT DELHI
DELHI
05.2025 - Current
- Project Scientist (Ongoing): Pursuing a research project titled “Novel Optical Fiber Technology for Quantum-enabled 6G Communication,” focused on advanced optical fiber design for quantum-compatible, next-generation communication systems.
- Industrial training of four months at the 220/132/33 KV Grid Station GLADNI, Jammu, J&K, on faults, power system protection, control and relay panel, and SCADA system.
Education
M.Tech - Quantum Computing
Defence Institute of Advanced Technology
Pune01.2025
B.E - Electrical Engineering
University of Jammu
Jammu, J&K01.2022
Higher Secondary -
Air Force School
Jammu, J&K01.2018
Secondary -
Air Force School
Jammu, J&K01.2016
Skills
- VHDL and Assembly language
- C and Python programming
- Quantum computing with Qiskit
- Deep learning with TensorFlow
- FPGA system design
- Xilinx tools expertise
- Embedded Linux development
- Digital design principles
- Quantum cryptography techniques
Projects
- Single Photon Avalanche Diode (SPAD) Design (Feb 2025)
Designed a PQAR-based SPAD with 40 ns TTL output and implemented PID-based real-time temperature stabilization. - Time Synchronization using PTP for QKD (Dec 2024)
Developed a PTP stack on Zynq ZCU102 MPSoC using Embedded Linux, generating PPS signals for precise time synchronization. - FPGA-based LDPC Error Reconciliation for QKD (Oct–Nov 2024)
Implemented a 5G-NR Base Graph-2 LDPC error correction scheme on FPGA for QKD post-processing. - Quantum Phase Fluctuation–Based QRNG (Feb–Jul 2024)
Implemented a Toeplitz hashing extractor on VC-709 FPGA, achieving 26.57 Gbps and validating randomness using NIST STS 2.1.2. - Switched Mode Power Supply Design (Mar 2023)
Designed a 220 V AC to 5 V DC SMPS using rectification and buck conversion with feedback-based regulation.
Publications
S.Chouhan, K. S. V. Anurag, G. Raghavan, P. Kanaka Raju, FPGA-based Toeplitz Strong Extractor for Quantum Random Number Generators, 2024 IEEE 5th India Council International Subsections Conference (INDISCON), Chandigarh, India, 2024, 1-5, 10.1109/INDISCON62179.2024.10744392
Accomplishments
Gold Medalist — M.Tech Quantum Computing, DIAT Pune (2025)
Conferences Workshops
- 5th IEEE India Council International Subsections Conference INDISCON 2024, 08/22/2024 - 08/24/2024, Presented Paper on 'FPGA-based Toeplitz Strong Extractor for Quantum Random Number Generators'.
- CDAC - International Workshop on 'Engineering and Integration Challenges in Quantum Communications and Quantum Computing', 03/21/2024 - 03/22/2024
Timeline
Project Scientist
Optics and Photonics Centre IIT DELHI
05.2025 - Current
M.Tech - Quantum Computing
Defence Institute of Advanced Technology
B.E - Electrical Engineering
University of Jammu
Higher Secondary -
Air Force School
Secondary -
Air Force School