Summary
Overview
Work History
Education
Skills
Websites
Accomplishments
Training
Timeline
Generic
SHUBHAM SRIVASTAVA

SHUBHAM SRIVASTAVA

Ghaziabad

Summary

Dynamic Senior Application Engineer with a proven track record at Synopsys India Pvt Ltd and Cadence Design Systems. Expert in runset development, including DRC, LVS, ERC and FILL, leveraging languages like PXL and PVL for nodes down to 3nm. Excelled in automating processes to enhance efficiency, showcasing strong problem-solving skills and a knack for innovation.

Overview

5
5
years of professional experience

Work History

SENIOR APPLICATION ENGINEER

SYNOPSYS INDIA PVT LTD
Noida
11.2021 - Current
  • Developed ERC/LVS/DRC runsets for different foundries using PXL (language used by ICV for 3nm, 4nm, 5nm, 16nm, 18nm, 28nm, 40nm 65nm, 130nm and 180nm nodes
  • Trained LLM models for generating new versions of the runset.
  • Developed and deployed packaging runsets.
  • Implemented custom flows tailored for specific requirements of the customers
  • Validated the quality of developed runset by checking code coverage and running QA using the testcases/IPs provided by the foundries
  • Implemented and deployed a LVS testcase generation flow which takes iPDK as input and generate LVS unit testcases for validating the quality of LVS runset
  • Deployed a DRC testcase generation flow that will generate the DRC unit testcases
  • Resolved multiple runset bugs on FULL CHIP and IP testcases
  • Automated multiple flows for reducing the TAT

SOLUTIONS ENGINEER

CADENCE DESIGN SYSTEMS
Noida
10.2020 - 11.2021
  • Written multiple FILL/DRC runsets for different foundries using PVL (language used by PVS/Pegasus) for 28nm, 22nm, 14nm, 12nm, 11nm 10nm 8nm 7nm and 5nm nodes
  • Validated quality of runset by checking code coverage and running QA using the testcases provided by the foundries
  • Automated multiple flows for reducing the TAT
  • Resolved runset issues on FULL CHIPs/IPs
  • Performed Tool runtime benchmarking on customer FULL CHIPs
  • Played a major role in getting Pegasus qualified on 4 nodes i.e., 22nm, 12nm, 7nm and 5nm
  • Implemented a FILL quality check flow for checking the improvement or degradation after the change in tool versions

SOLUTIONS INTERN

CADENCE DESIGN SYSTEMS
Noida
11.2019 - 09.2020
  • Written DRC runsets for different foundries using PVL for nodes including 28nm, 14nm, 11nm, 10nm and 8nm
  • Validated the quality of runset by checking code coverage and running QA using foundary provided testcases
  • Automated a FILL QA report generation flow

Education

B.Tech. - Electronics and Communication Engineering

INDERPRASTHA ENGINEERING COLLEGE
06.2019

12TH -

NEW RAINBOW PUBLIC SCHOOL
05.2015

10TH -

NEW RAINBOW PUBLIC SCHOOL
04.2013

Skills

Runset Development

  • DRC
  • LVS
  • FILL
  • ERC

Tools

  • IC Validator
  • ICVWB
  • Custom Compiler
  • Pegasus
  • PVS
  • Virtuoso

Scripting

  • Python
  • TCL
  • TCSH
  • Bash
  • Awk
  • Sed

Accomplishments

  • Runner Up ACE 2023 in 'Outstanding award for innovation' category
  • Project Warrior Award 2024
  • Project Warrior Award 2023

Training

ASIC Design and Full Custom Layout Training, Pine Training Academy

Timeline

SENIOR APPLICATION ENGINEER

SYNOPSYS INDIA PVT LTD
11.2021 - Current

SOLUTIONS ENGINEER

CADENCE DESIGN SYSTEMS
10.2020 - 11.2021

SOLUTIONS INTERN

CADENCE DESIGN SYSTEMS
11.2019 - 09.2020

B.Tech. - Electronics and Communication Engineering

INDERPRASTHA ENGINEERING COLLEGE

12TH -

NEW RAINBOW PUBLIC SCHOOL

10TH -

NEW RAINBOW PUBLIC SCHOOL

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