Sidhant Bhattacharyya

• Designed a top level sub-system floorplan consisting of 370 RAM's and ECC memories flattening dual IP's in 16ffc technology.
• Hierarchical partitioning of sub-system to reduce runtimes and top level port placement based on the bus communications to the NOC.
• Executed baseband IP using the RTL2GDS methodology in Fusion Compiler and carrying out the related verification checks (LEC/PDN/PDV/STA).
• Took part in constraint generation and feedbacks as an exercise to port a set of modular constraints to make it compatible to Cadence toolset.
• Co-developed an utility to get an estimate of the track utilization in the design with GUI visualization.
• Completed Automotive Functional safety ISO26262 certification from TUV SUD Germany.

Tech Nodes: 16ffc, 5nm

• HPC core implementation(Cortex 7 series) to push frequency using native tool ML integration.
• Performed TAT reduction exercise using guidance from auto macro placer building floorplan constraints for ~400 macros and restricting netlist growth to 3M instances at post-route leading to successful tapeout.
• Methodology evaluation and Flow deployment (power aware placement/flexible H-tree) for multi-million gated Ghz designs to achieve best possible closure techniques and best in class PPA.
• Precision debug and analysis of all APR stages to resolve congestion and application issues.

Tech Nodes: 8lpp, 7nm and 28 FDSOI

• Successful tapeout on 8LPP technology with PnR rework on clock tree and final timing closure on multiple setup/hold corners.
• Successful tapeout (Netlist2GDS) on 28nm of audio segment DSP core, with large L2 cache implementation being a major challenge.
• Floor planning of a high-speed multi power domain notch block leading to a successful 7nm tapeout reaching a target frequency of 3Ghz.

• Executed Netlist-GDS2 flow and physical verification of graphic cores for Intel's Gemini Lake and Canon Lake programs.
• DRC/ERC/LVS fixes at partition level for PDV signoff.
• Timing ECO fixes to fix setup/hold violations.

• RTL verification intern: Performed Test-bench porting from Verilog to UVM.