Siddhant Verma

Physical Design (PnR) Engineer -3nm & 2nm Tech Node | Cadence Innovus

• Executed end-to-end PnR implementation for high-performance SoC blocks at the 3nm technology node using Innovus, ensuring robust design closure.
• Developed and optimized floorplans, placement, and clock tree synthesis strategies to meet PPA targets.
• Resolved timing DRC violations within the block to ensure sign-off compliance.
• Successfully delivered on-time tape-out with zero critical violations, meeting aggressive schedule milestones.

Physical Design (PnR) Engineer -5nm Tech Node | Cadence Innovus

• Resolved dynamic IR drop issues in the critical block, improving power integrity.
• Achieved LVS and DRC clean sign-off by systematically addressing violations.
• Resolved density issues in block layout to meet requirements.
• Worked as an STA Engineer for timing closure at 983 MHz, collaborating with design and sign-off teams for successful closure.

• Advised students on resume writing and interview preparation techniques.
• Maintained accurate records of applicants, placements and employer contacts.