Siri S

Highly-motivated individual with desire to take on new challenges. Strong work ethic, adaptability and exceptional interpersonal skills. Committed to punctuality, accuracy and streamlining processes for increased productivity.

I aspire to play roles of significance in organizations wherein I can add value to the work and lives of people around.

Title: DESIGN AND VERIFICATION ENGINEER

• English
• Kannada
• Hindi

• Dancing
• Drawing
• Swimming
• Writing poems

• Router 1x3 - RTL Design and Verification.

The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2., Architected the block level structure for the design. Implemented RTL using Verilog HDL, synthesized the design,verified using UVM based testbench environment.

• AHB2APB Bridge IP Core Verification

The AHB to APB bridge is an AHB slave which works as an interface between the high speed     AHB and the low performance APB buses., Architected the class based verification environment in UVM, Verified the RTL module with UVM Test Bench with different test scenarios like single READ, WRITE & Burst READ, WRITE with different burst lengths 

• Mod12 Counter

RTL Design and Verification, Implemented RTL using Verilog HDL. Verified using System verilog HVL based testbench environment. Generated code coverage for the RTL design.

• Solar wireless electric vehicle charging system:

Wireless charging for Electric Vehicles utlizes the principle of electromagnetc induction or resonant coupling to  transfer electrical energy from a charging pad or station to the vehicle's onboard battery without the need for physical cables.

I hereby declare that the details furnished above are true and correct.

• Participant of the official World record attempt of Largest Bharathanatyam Dance .

https://drive.google.com/file/d/1Tnqa4QO1lWnsNysn9Ie3H1FuAGrTxSL3/view?usp=drive_link