Siva Prasad Sripathi
Summary
Ph.D. in Electronics and Communication Engineering with 3.5 years of industry experience and 5 years in academia. Proven ability to solve complex problems and develop scalable hardware architectures using advanced technologies. Expertise in RTL design, verification, and architectural modeling, with a focus on applying theoretical knowledge to practical industry challenges. Strong communication skills and commitment to continuous improvement drive professional growth and team success.
Overview
16
16
years of professional experience
Work History
Assistant Professor
KL University
Vijayawada
06.2023 - Current
- Department of ECE
Assistant Professor
QIS College of Engineering and Technology
Ongole
11.2012 - 01.2016
- Department: Electronics and Communication Engineering
DFT Engineer
Qualcomm
Bangalore
04.2011 - 11.2012
- Contributed to the Design-for-Test (DFT) implementation for Snapdragon SoCs at advanced process nodes .
- Performed scan implementation and optimization across multiple logic blocks to enable effective testability.
- Enhanced structural test coverage by analyzing fault models, and improving scan and control logic.
- Generated and simulated Automatic Test Pattern Generation (ATPG) patterns targeting stuck-at and transition faults.
- Conducted timing analysis and constraint validation to ensure scan timing closure and test mode functionality.
- Collaborated with cross-functional teams to integrate DFT architecture.
Design Engineer
Delphi, Technical Centre India
Bangalore
08.2009 - 03.2011
- Embedded Hardware development activities for clusters and Body control modules for automobiles
- Design of DC/DC converter using Boost Topology
- Design verification by testing proto board and by simulation using saber tool
- Process related activities in the project time line from sample build till production
Education
Ph.D - VLSI-Signal Processing
NIT Warangal
Warangal05-2024
M.Tech - Microelectronics and VLSI Design
NIT Calicut
05-2009
B.Tech - Electronics and Communication Engineering
SIET (JNTU)
Nuzvid, A.P.01.2006
Skills
- RTL Design & Microarchitecture – Proficient in Register-Transfer Level (RTL) design using SystemVerilog/Verilog for developing high-performance, low-power digital subsystems and custom logic blocks
- Digital Logic Design – Strong foundation in synchronous digital design principles, pipelining, FSMs, datapaths, and control logic implementation
- Functional Block Development – Experience in designing and integrating key components such as ALUs, FPUs, caches, memory controllers, interrupt logic, crypto engines, PCIe interfaces, and DLLs
- Timing Analysis & Design Verification – Skilled in static timing analysis (STA), clock domain crossing (CDC) checks, linting, synthesis, and formal verification for robust design signoff
- Low-Power Design Methodologies – Application of clock gating, power gating, multi-Vt strategies, and UPF-based power intent modeling for power-aware logic design
- Project Execution & Team Collaboration – Experience in Agile methodologies, including sprint planning, cross-functional teamwork, and iterative feature development
- EDA Tools & Workflows – Hands-on with industry-standard tools: Synopsys Design Compiler & PrimeTime, Spyglass, VCS, QuestaSim, Verdi; proficient in Git, Jira, and collaborative development workflows
Timeline
Assistant Professor
KL University
06.2023 - Current
Assistant Professor
QIS College of Engineering and Technology
11.2012 - 01.2016
DFT Engineer
Qualcomm
04.2011 - 11.2012
Design Engineer
Delphi, Technical Centre India
08.2009 - 03.2011
Ph.D - VLSI-Signal Processing
NIT Warangal
M.Tech - Microelectronics and VLSI Design
NIT Calicut
B.Tech - Electronics and Communication Engineering
SIET (JNTU)
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