Sonakshi Kanchgar

Methodical Design Verification Engineer with expertise in SV and UVM methodologies. Developed test plans and tests, specializing in Constrained Random verification, Functional coverage, and Assertions based testing. Experienced in IP Level and SOC level verification at companies including Wipro and Intel.

• Platform Controller Hub(PCH), 1.8 years, wipro(odc-Intel), VNC, The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. These include clocking (the system clock), Flexible Display Interface (FDI) and Direct Media Interface (DMI), although FDI is used only when the chipsets is required to support a processor with integrated graphics. As such, I/O functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller and PCIe lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge., Worked on TypeC IP, Verified different tests on TypeC IP, Worked on SAFS, Developed few tests and verified the tests on SAFS
• Verification of PCIE4.0 SOC Verification In UVM using system Verilog, 1.5 years, texus, Verdi, Perforce, PCIe (peripheral component interconnect express) is an interface standard for connecting high-speed components. Every desktop PC motherboard has a number of PCIe slots you can use to add GPUs (aka video cards aka graphics cards), RAID cards, Wi-Fi cards or SSD (solid-state drive) add-on cards., Worked on the DLLP and ACK/NAK protocol for error correction, Verified different packets like posted/non posted requests, Checked different scenarios of ACK generation and NAK generation
• AXI4.0 VIP development in UVM using system Verilog, 11 months, Agasthya/ACL, Questasim, The Advanced eXtensible Interface (AXI), part of the ARM Advanced Microcontroller Bus Architecture 3 (AXI3) and 4 (AXI4) specifications, The AMBA AXI protocol supports high-performance, high-frequency system designs., Implemented the transaction item with appropriate Constraints and Sequences for AXI bus, Wrote coverage block to capture the coverage signals, Coded Coverage and Assertions to verify the functionality of the design, Verified the all the features as per the AXI specification

BE, Electronics and Communications, Basaveshwar Engineering college(VTU), Bagalkot, 2018, Board of Pre-University Education, 2014, KSEEB, 2012

UVM, SV, C++, Verilog, VHDL, PCIE4, AXI4, SOC, IP verification, VCS, VNC, Verdi, Perforce, JIRA, Perforce and Clear case

• Embracing a variety of interests and skills.
• Balancing personal and professional life.
• Volunteering: Actively volunteer at a local community center, organizing weekly activities for underprivileged children, which showcases my commitment to social responsibility and community engagement.
• Sports: Participated in branch-level cricket tournaments and won first prize, ability to stay physically active while managing a busy schedule.
• Music: Self-taught guitarist, regularly perform at local events, highlighting creativity and dedication to personal growth outside of professional work.

• IP Verification Success: Led the verification of a IP core using Universal Verification Methodology (UVM) and SystemVerilog (SV), achieving 100% functional coverage.
• PCIe Verification: Successfully verified multiple PCIe-based designs, using advanced UVM testbenches, significantly reducing time-to-market for the products.
• Recognition for Excellence: Awarded “Outstanding Contributor” by [Agasthya App Labs Pvt Ltd] for delivering a critical IP block verification ahead of schedule.

VLSI Design and Verification

Sandeepani school of embedded system design - Mar 2019 - Jan 2020

Certification of Professional Development Course(PDC) in VLSI Design and Verification.