Sreekala Puduru
Bengaluru
Summary
- Adaptable Software Engineering Manager keen to wrangle multiple simultaneous projects into streamlined, cohesive and profitable efforts. .
- Experienced Engineering professional with close to 14 years of work experience across MNCs spanning hardware and software areas
- Thrives on providing exceptional oversight and hands-on guidance guaranteed to improve throughput figures and quality metrics.
- 5 years of Technical Engineering Management experience with proven track record of delivering and driving projects from incubation to deployment.
- Certified ScrumMaster with experience in managing multiple scrum teams and projects.
- Experienced professional with experience in all cycles of product development including high-level, low-level designs, development and verification in large scale VLSI systems, Cloud Native networks orchestration and automation solutions.
- Product Engineer with over 6 years experience. Areas of expertise include ATE equipment programming and operation of TI-VLCT and LTX-Fusion.
- Dual Masters in Computer Engineering and Electrical Engineering.
Overview
21
21
years of professional experience
Work History
Technical Lead Project Manager
Anuta Networks India
08.2018 - Current
- Planned and managed releases and deployment drops for STOC, Iberdrola, NEC
- Pro-active engagement with account teams and TMEs for a smooth deployment experience through daily inter-locks
- Release planning with PLM and Dev teams for the roadmap items
- Daily scrums and weekly bug scrub calls with streamlined tracking of metrics and trends
- Contributed to testing automation for a number of testing suites over the years
- Actively engaged in bug fixes, development tasks, and raising bugs too
- Familiar with CI/CD methodologies and environment
- Intermediate expertise with NetConf/Yang, Grafana, Prometheus, Influx DB, Groovy and Robot framework
- Familiarity with Kubernetes, Network Automation and Orchestration solutions
- Good familiarity and regular user of JIRA tool
Technical Program Manager
Formac Inc
03.2016 - 07.2018
- Technical project Manager for the flagship products of Formac called "ePracto" and "eYardstick"
- Co-ordinated campus hiring events across multiple engineering colleges across Karnataka and AP
- Developed and implemented curriculum and training materials appropriate for college grads for their test and interview preparation
- Planned and managed training projects for clients (Engineering colleges)
- Regularly reviewed training materials and courses to ensure updates were included within a reasonable timeframe
- Weekly project meetings with clients to get an active feedback pipe back into the training materials
- Active scouting of potential hiring companies to match the student profiles
Product Engineer
Texas Instruments Incorporated
08.2006 - 06.2011
- Developed Standardized ATE Test Routines to support 0 DPM Automotive requirements.
- Expertise in designing, developing, debugging, auditing and maintaining test programs.
- Proficient in Enabling Multi site Testing Capability by strategically assigning ATE Resources (Power & Mix Signal components) to Load Board.
- Experienced in advanced device debug through analysis and interpretation of data generated from the test platform.
- Reviewed DFT Spec to support Post Si Testing – MBIST, PBIST, LBIST & ATPG Testing.
- Experienced in developing test hardware (PCB boards) for mass production on ATE, this includes designing schematic, reviewing placement and routing. Approval for schematics is done using an Agile review.
- Collaborated successfully with cross-functional development teams to design and manufacture new products.
- Proficient in performing data analysis at wafer and package level using tools like TI-dataware, spotfire etc.
- Received training on LTX Fusion and TI-internal test engineering (VLCT) platforms.
- Proficient in handling probe and packaged die projects on multiple test platforms.
Research Assistant
The University of Texas at Dallas
06.2004 - 07.2006
- Worked as a research assistant in the High Performance Dependable Computing Lab.
- Major research areas include Power Efficient Architectures, Embedded Architectures, Fault Tolerance, Chip Multiprocessors, Reconfigurable Computing and Digital IC design.
- Prepared materials for reports, presentations, and submission to peer-reviewed journal publications.
- Performed statistical, qualitative and quantitative analysis.
- Sreekala Puduru, Hui Wang and Rama Sangireddy, "A scalable scheme for dependable cache consistency architecture in wireless ad-hoc networks", in Proceedings of First IEEE International Workshop on Next Generation Wireless Networks, WoNGeN-2005, December 2005
Testing Engineer
SVTRONICS Inc.
03.2003 - 05.2005
- Tested PCB prototypes using CONDOR, a flying probe tester that does in-circuit and functional testing.
Education
Master of Science - Computer Engineering
The University of Texas at Dallas
Richardson, TX2007
Master of Science - Electrical Engineering
The University of Texas at Dallas
Richardson, TX2005
Bachelor of Technology - Electrical and Electronics Engineering
Sri Venkateswara University College of Engineering
Tirupati, AP1999
Skills
- Network Management
- Closed Loop Automation
- Telemetry & Analytics
- Multi-Vendor Network Orchestration
- Kubernetes & Docker
- Grafana/Prometheus
- Robot Framework
- Groovy Scripts
- Physical Design
- VHDL, SPICE, Synopsis Design Complier
- Cadence-Virtuoso Layout Editor, Magic
- IC Design & Synthesis
- Product Engineering of IC
Timeline
Technical Lead Project Manager
Anuta Networks India
08.2018 - Current
Technical Program Manager
Formac Inc
03.2016 - 07.2018
Product Engineer
Texas Instruments Incorporated
08.2006 - 06.2011
Research Assistant
The University of Texas at Dallas
06.2004 - 07.2006
Testing Engineer
SVTRONICS Inc.
03.2003 - 05.2005
Master of Science - Computer Engineering
The University of Texas at Dallas
Master of Science - Electrical Engineering
The University of Texas at Dallas
Bachelor of Technology - Electrical and Electronics Engineering
Sri Venkateswara University College of Engineering
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