Srikanth Sistla
Bangalore,KARNATAKA
Summary
With 6.5+ years of experience in Physical Design, seeking and maintaining a full-time position that offers professional challenges while utilizing interpersonal skills, excellent time management, and problem-solving abilities in the field.
Overview
8
8
years of professional experience
2
2
years of post-secondary education
Work History
Senior Physical Design Engineer
ARM Embedded Technologies
BANGALORE
04.2024 - Current
- Working on l2misc partition of arm big-core in SF2P node with a target frequency of 4 Ghz and is in stable progress .
- Worked on Perseus POP (intel customer) in N3P node @ 3Ghz .FCI analysis, FSDB generation, x-replay settings understood & runs performed .
- Multiple qor runs with different floorplans done & successfully achieved the target qor for beta release .
- PNR & PT setup done initially using the reference scripts .
- Working on l2misc partition of arm big-core in SF2P node with a target frequency of 4 Ghz and is in stable progress .
- Managed to do flow testing & tech node studies with the existing scripts & flow.
STAFF PHYSICAL DESIGN ENGINEER
Maxlinear Technologies Pvt. Ltd.
Bangalore
03.2020 - 03.2024
- Worked on floor planning, PNR for block & sub-system level, handling DDRSS, PV(top level & block level), STA(block level),EM/IR(block level)
- Block closure with all fixes in Timing, EM/IR, PV & other checks for final closure
- Performed top-level PV checks/closure for 5nm, Pad-ring placement & checks, ESD-concept_review/diagram
- Understanding of UPF, CDC, Timing constraints and basic DFT concepts
- Currently, working on DDR4 sub-system block with a period of 1.35ns for PnR (800 instances)
- Worked along with synopsys for implementing DDR 4/3 PHY IP
- Built the clock tree(pub-logic) with synopsys constraints on multiple clocks, maintaining required latency & skew
- Also, Timing closure, PV checks, EM/IR & resistance checks done on the sub-system
- Completed RTL to GDSII for the dpd block (2.7 million instances) in the same project
- Worked on PathFinder-SC & soc evaluation by finding resistance on IO pads & ESD-clamps
- Developed a flow using python and able to successfully verify the resistance numbers
- Working on DRC (base checks) & LVS at block levels, debugging & giving feedback fixes on block basis & and closed it for N1,N2 phases (Worked as PV lead)
- Handled on top-level DRC checks, Bump checks, IO related checks, Base & Metal fill checks, Antenna checks, pad-ring LVS and also used the utilities DRC (recon, inverse-recon), RTD, Gray Box
- Tools used: Innovus, ICC, ICC2, Aprisa, Tempus, PrimeTime, PathFinder-soc, PathFinder-SC, Redhawk, Tango, Genus, Design compiler (DC), Calibre(DesignRev, RVE)
Digital Design Engineer
Intel Technology India Pvt. Ltd.
Bangalore
07.2017 - 02.2020
- Synthesis, Floorplanning, PNR, Timing convergence/fixes for blocks, (FEV) checks, RV & quality checks at the block level for intel foundry specific
- Responsible to meet both timing and power targets at very high frequency (flat, latch-based designs) of 4.2 GHZ
- Congestion issues, IR drop violations, DRC, timing, power and quality checks met within time
- Full synthesis & PNR of the blocks & timing checks using Tango
- Responsible to close the timing targets, quality checks and FEV
- Also fixed speed paths after PSD, accommodated the bug fixes in ECO's
Education
Masters - RF & Microwave
IIT KANPUR
Kanpur 07.2015 - 07.2017
Skills
Good Understanding of SF2P,N3P, N5, N7, N16 technologies of TSMCExperience in SynthesisPNRTiming analysis (STA)Physical verification (PV)EM/IRUPF conceptsCDCExpertise in physical verification and signoffFamiliarity with TclPythonUnixUnderstanding of flowsTools & methodologiesFunctional/clocking diagram generation
undefinedTimeline
Senior Physical Design Engineer
ARM Embedded Technologies
04.2024 - Current
STAFF PHYSICAL DESIGN ENGINEER
Maxlinear Technologies Pvt. Ltd.
03.2020 - 03.2024
Digital Design Engineer
Intel Technology India Pvt. Ltd.
07.2017 - 02.2020
Masters - RF & Microwave
IIT KANPUR
07.2015 - 07.2017
Similar Profiles
Vidya RamanarayananVidya Ramanarayanan
Principal Verification Engineer at ARM Embedded TechnologiesPrincipal Verification Engineer at ARM Embedded Technologies
Rudrapratap RoyRudrapratap Roy
Verification Engineer at ARM Embedded TechnologiesVerification Engineer at ARM Embedded Technologies
Mohamed Fashil MMohamed Fashil M
Senior Sourcing Partner at ARM Embedded TechnologiesSenior Sourcing Partner at ARM Embedded Technologies