Summary
Overview
Work History
Education
Skills
Accomplishments
ACADEMIC PROJECTS
Timeline
Generic
Sristi Ghosh

Sristi Ghosh

Kolkata

Summary

Electronics and Communication Engineering undergraduate with a strong foundation in Digital Design and Verilog HDL. Skilled in designing and understanding combinational and sequential circuits, counters, flip-flops, registers, and FSM-based systems. Hands-on experience with basic RTL design and simulation using Verilog. Eager to begin a career in VLSI and contribute to reliable hardware solutions.

Overview

1
1
year of professional experience

Work History

Summer Intern

IIEST Shibpur
Howrah
06.2026 - 08.2026
  • Tools learned: Openroad, Icarus verilog, GTKwave, yosys, openlane.
  • Worked as a research intern on open-source RTL-to-GDSII physical design flow.

Winter Intern

Jadavpur University
Kolkata
12.2025 - 02.2026
  • Tools learned: Cadence Virtuoso, FPGA, Synopsys EDA tool, Xilinx Vivado.
  • Worked under IC Design and Fabrication Centre, Electronics and Tele-Communication Engineering Department . Learned about design flow, analog and digital circuits. Implemented several logics on FPGA. Analog device design on cadence virtuoso and modelsim and simulated its working results.

Education

B.Tech - Electronics and Communication Engineering

Heritage Institute of Technology
Kolkata

Higher Secondary Education -

Holy Cross School
Kolkata

Secondary Education -

Holy Cross School
Kolkata

Skills

  • Java
  • Python
  • C
  • Verilog
  • Jupyter notebook
  • Xilinx Vivado
  • Cadence Virtuoso
  • Matlab
  • LTspice
  • Arduino IDE

Accomplishments

  • 3rd Position in Tech Knights 2.0 Hardware Project Competition, Secured 3rd Position in the Tech Knights 2.0 Hardware Project Competition held at Heritage Institute of Technology.
  • Judge's Choice Award in AI-In-Hardware: Smart System Design Challenge 2025, Received the Judge's Choice Award in AI-In-Hardware: Smart System Design Challenge 2025, organized by IEEE MTT-S HITK SBC and ECE Department, HITK in association with IEEE AP-MTT Joint Chapter, Kolkata Section.

ACADEMIC PROJECTS

  • Mod-5 Synchronous and Asynchronous Up Counter: Designed and implemented a 3-bit synchronous and asynchronous Mod-5 up counter using Verilog HDL., Implemented clock-based state transitions with reset functionality., Developed a basic testbench to verify normal counting and reset operation. Done its synthesis using yosys and the layout. Tools:Verilog HDL, Icarus Verilog, GTKWave, Openroad.
  • 1101 Sequence Detector using Mealy FSM: Designed a finite state machine to detect the overlapping binary sequence 1101., Developed the state transition and output logic using Verilog HDL. Implemented the FSM using sequential and combinational logic. Verified state transitions and sequence detection using a Verilog testbench and waveform simulation. Tools: Verilog HDL, Icarus Verilog, GTKWave.
  • FINFET Technology (18nm) Based VLSI Multiport Register File :Final year ongoing project.
    Enabling simultaneous read/write operations for high-speed processor by 8T SRAM.Studied the operation of FinFET devices and their suitability for low-power and high-performance VLSI circuits. Implemented register-file architecture using memory cells, read/write circuitry. Tools: Cadence Virtuoso.

Timeline

Summer Intern

IIEST Shibpur
06.2026 - 08.2026

Winter Intern

Jadavpur University
12.2025 - 02.2026

B.Tech - Electronics and Communication Engineering

Heritage Institute of Technology

Higher Secondary Education -

Holy Cross School

Secondary Education -

Holy Cross School
Sristi Ghosh