Summary
Overview
Work History
Education
Skills
Accomplishments
Technical Summary
Publications
Training
Timeline
Generic

SRUTHI PK

Bangalore

Summary

Tech-savvy professional with advanced training and 5+ years experience in various stages of FPGA synthesis and tool validation. Delivers excellent results to delight customers and drive internal enhancements. Always seeking new and improved strategies to achieve objectives.

Overview

6
6
years of professional experience

Work History

Application Engineer Sr I

Synopsys (India) Pvt. Ltd
Bangalore
01.2019 - Current
  • Working for Xilinx mapper product validation team
  • Responsible for Xilinx mapper validation (Synthesis + P&R) for new features in Synplify premier/Pro and single FPGA flow for HAPS devices using protocompiler
  • Responsible for developing test-cases for feature validation and regressions
  • Responsible for Analyzing the logical as well as QoR issues and report if the issue needs to be fixed by developer
  • Handling different enhancement request by the customers
  • Responsible for Regression testing.

Intern (Technical-Engineering)

Synopsys (India) Pvt. Ltd
Bangalore
01.2018 - 01.2019
  • Understood the DSP architecture of Xilinx Ultrascaleplus devices and verified if the tool optimizes the designs as required
  • Validated the functionality by performing RTL v/s mapped netlist simulation
  • Analyzed the logical and QoR issues and reported.

Education

B.Tech - Electronics And Communication -

CUSAT,Cochin, Kerala
06.2010

M.Tech VLSI Design -

Amrita Viswavidyapeedam, Bangalore Campus.

Skills

  • Application Debugging
  • Cross-Functional Collaboration
  • Efficiency Improvement
  • Quality Assurance
  • Technical Troubleshooting
  • Specification Development
  • Verbal and Written Communication

Accomplishments

· “TileNET: Hardware accelerator for ternary Convolutional Neural Networks” in the journal Microprocessors and Microsystems, Volume 83, 2021.

Presented the paper “Implementation of Multipliers using Stacker based Binary Compressors” in International Conference Electrical, Electronics, Communication, Computers and Optimization Techniques (ICEECCOT-2018) and have been awarded as the “Best Paper Presenter.”

Technical Summary

Hardware description language: Verilog, Systemverilog. Operating system: Windows, Linux Scripting language: Shell, Python,TCL

Tools: Synplify Premier/Pro, Protocompiler, ProtoSynthesis, Xilinx Vivado, VCS

Publications

TileNET: Hardware accelerator for ternary Convolutional Neural Networks Implementation of Multipliers using Stacker Based Binary Compressors

Training

Mentor Graphics System Verilog Training Program 2017, 06/15/2017, 07/28/2017

Timeline

Application Engineer Sr I

Synopsys (India) Pvt. Ltd
01.2019 - Current

Intern (Technical-Engineering)

Synopsys (India) Pvt. Ltd
01.2018 - 01.2019

B.Tech - Electronics And Communication -

CUSAT,Cochin, Kerala

M.Tech VLSI Design -

Amrita Viswavidyapeedam, Bangalore Campus.
SRUTHI PK