SRUTHI PK

Tech-savvy professional with advanced training and 5+ years experience in various stages of FPGA synthesis and tool validation. Delivers excellent results to delight customers and drive internal enhancements. Always seeking new and improved strategies to achieve objectives.

· “TileNET: Hardware accelerator for ternary Convolutional Neural Networks” in the journal Microprocessors and Microsystems, Volume 83, 2021.

Presented the paper “Implementation of Multipliers using Stacker based Binary Compressors” in International Conference Electrical, Electronics, Communication, Computers and Optimization Techniques (ICEECCOT-2018) and have been awarded as the “Best Paper Presenter.”

Hardware description language: Verilog, Systemverilog. Operating system: Windows, Linux Scripting language: Shell, Python,TCL

Tools: Synplify Premier/Pro, Protocompiler, ProtoSynthesis, Xilinx Vivado, VCS

TileNET: Hardware accelerator for ternary Convolutional Neural Networks Implementation of Multipliers using Stacker Based Binary Compressors

Mentor Graphics System Verilog Training Program 2017, 06/15/2017, 07/28/2017