Sufiyan Amdani

Description: The Qualcomm Hexagon processor is a digital signal processor (DSP) designed for high-performance and low power consumption across a wide variety of multimedia and modem applications.

Roles and Responsibilities:

• CDC and Fishtail SVA Integration and Testing.
• Developed and integrated System Verilog Assertions (SVAs) for the core verification environment.
• Conducted regression tests using SVAs and debugged any assertion failures that occurred.
• Conducted core bring-up by enabling automatic jobs, tracking regressions, and debugging failures.
• Proficient in regression test case analysis, benchmark failure analysis, and debugging regression setups using Jira.

Description: RASIP is a central resource on any SOC that provides a scalable and modular way of logging and escalation of errors.

Roles and Responsibilities:

• Understanding the RASIP Design specification.
• Developed sequences and tests as per the test plan to verify the functionality
• Debugging the failing tests in regression as per the flow.
• Added new scenarios as per delta changes
• Worked on IPC tests to verify functionality of the Error flow.

Description:

AVST is used for components that drive high-bandwidth, low-latency, unidirectional data. Typical applications include multiplexed streams & packets. It is a system of one or more Avalon-ST connections that transmit data from a source interface to a sink interface.

Roles and Responsibilities:

• Understanding the test plan.
• Verified the RTL by creating different test cases according to the test plan, with & without backpressure.
• Getting 100% coverage for some scenarios of data transmission through multiple channels and for the error signal.

Description:

This clock reset control unit is used to generate different clocks and resets for different blocks like spu, cpm, debug unit etc., with multiple different clock frequencies for each block connected with it.

Responsibilities:

• Worked on the test case and test sequence enhancement
• Verified the fault tolerance of CRCU by injecting faults
• Ran regressions and debugged failing tests