Experienced hire with over 3 years of talent acquisition and installation experience, specializing in supporting RTL design using Verilog.
Hardworking and passionate individual with strong organizational skills seeking an entry-level RTL Design Engineer position.
Motivated team player with excellent verbal communication skills, eager to adapt to new challenges and contribute to organizational success.
Overview
5
5
years of professional experience
2017
2017
years of post-secondary education
2
2
Certifications
3
3
Languages
Work History
Trainee
Maven Silicon
12.2023 - 12.2024
Completed comprehensive training in RTL design principles and methodologies, focusing on industry-standard practices.
Developed proficiency with industry-standard EDA tools like Synopsys- VC SpyGlass, Design Compiler, Mentor-QuestaSim, through hands-on labs and projects.
Successfully applied learned concepts to projects like RISC-V RV32 Multistage pipeline processor, Router1x3 design.
Technical Recruiter
Qcentrio
08.2022 - 05.2023
Collaborated closely with hiring managers to understand technical requirements and align talent acquisition strategies accordingly.
Used Boolean searches to develop applicant portfolios for expected openings.
Conducted phone interviews to assess applicants relevant knowledge, skills, experience and aptitudes.
Maintained accurate records of all recruitment activities and provided regular updates to manager on progress towards hiring goals.
System Engineer
Virtuous Screening Pvt.Ltd
04.2020 - 06.2022
Managed use of various types of databases and configured, installed and upgraded new ones.
Provided expert support for end-users, ensuring optimal system performance and user satisfaction.
Education
B.Tech - Electronics & Communication Engineering
VLITS, JNTUK University
06-2016
Skills
Verlog
Certification
VLSI Design Methodologies from Maven Silicon.
Timeline
Advanced VLSI Verification Certification from Maven Silicon.