An extremely motivated and thorough MTech graduate with practical Design for Testability (DFT) experience, including the development of SCAN, ATPG, and IDDQ. worked on industry-standard DFT environments for intellectual property. Strong foundation in both analog and digital IC design, RTL design, static timing analysis (STA), and physical design methodologies. Skilled in using advanced EDA tools, such as Cadence Virtuoso, Modus, and AMD Vivado. I'm eager to show a strong commitment to semiconductor innovation and a keen interest in integrated circuit design, verification and testing. Ready to offer creative VLSI design teams technical expertise and a problem-solving methodology.
Gained hands-on experience in Design for Testability (DFT), focusing on the generation and integration of IDDQ, SCAN, and ATPG test structures to enhance test coverage and fault detection efficiency. Extensively involved in the functional testing of a complex IPs within industry standard DFT environment, debug analysis to validate design functionality under test conditions. Demonstrated a strong understanding of DFT methodologies and contributed to improving the testability and reliability of the design.
● FIFO: A First In, First Out (FIFO) buffer memory is utilized for exchanging data between clock domains. The FIFO code is developed using Verilog HDL and incorporates underflow and overflow detection techniques to prevent incorrect data passing. FIFOs can be either synchronous or asynchronous.
● Two Stage OPAMP: Designed a two-stage operational amplifier featuring a differential amplifier followed by a gain stage. Used a common-source amplifier for the second stage. This configuration offers high gain, better stability, and improved bandwidth. Utilized Miller compensation to ensure stability and optimize performance.
● DAACA: Digital Automatic Automobile Counting Apparatus (Major): In this project, an automobile vehicle counter apparatus was built using Verilog HDL. The apparatus was designed to count and display the "total spots" and "vacant spots" inside a parking area. All hardware simulation was performed in Vivado and implemented on the Basys 3 FPGA Board.