Summary
Overview
Work History
Education
Skills
Projects
Languages
Certification
Accomplishments
Affiliations
Timeline
Generic
SUMIT KUMAR

SUMIT KUMAR

Bengaluru

Summary

An extremely motivated and thorough MTech graduate with practical Design for Testability (DFT) experience, including the development of SCAN, ATPG, and IDDQ. worked on industry-standard DFT environments for intellectual property. Strong foundation in both analog and digital IC design, RTL design, static timing analysis (STA), and physical design methodologies. Skilled in using advanced EDA tools, such as Cadence Virtuoso, Modus, and AMD Vivado. I'm eager to show a strong commitment to semiconductor innovation and a keen interest in integrated circuit design, verification and testing. Ready to offer creative VLSI design teams technical expertise and a problem-solving methodology.

Overview

1
1
Certification

Work History

Digital Design Eng Intern

Texas Instruments
Bengaluru
01.2025 - 07.2025

Gained hands-on experience in Design for Testability (DFT), focusing on the generation and integration of IDDQ, SCAN, and ATPG test structures to enhance test coverage and fault detection efficiency. Extensively involved in the functional testing of a complex IPs within industry standard DFT environment, debug analysis to validate design functionality under test conditions. Demonstrated a strong understanding of DFT methodologies and contributed to improving the testability and reliability of the design.

Education

Master of Technology - VLSI System

National Institute of Technology
Tiruchirappalli
06-2025

Bachelor of Technology - Electronics And Communication Engineering

Ujjain Engineering College
Ujjain
06-2023

Class 12th - PCM

Central Public School
Samastipur
03-2018

Class 10th -

Holy Mission High School
Samastipur
03-2016

Skills

  • Digital IC design
  • Analog IC design
  • Verilog HDL/RTL design
  • Physical design
  • Static timing analysis
  • ASIC flow
  • Problem solving
  • Technical documentation

Projects

FIFO: A First In, First Out (FIFO) buffer memory is utilized for exchanging data between clock domains. The FIFO  code is developed using Verilog HDL and incorporates underflow and overflow detection  techniques to prevent incorrect data passing. FIFOs can be either synchronous or asynchronous.  

Two Stage OPAMP: Designed a two-stage operational amplifier featuring a differential amplifier followed by a gain stage.  Used a common-source amplifier for the second stage. This configuration offers high gain, better  stability, and improved bandwidth. Utilized Miller compensation to ensure stability and optimize  performance.  

DAACA: Digital Automatic Automobile Counting Apparatus (Major): In this project, an automobile vehicle counter apparatus was built using Verilog HDL. The apparatus  was designed to count and display the "total spots" and "vacant spots" inside a parking area. All  hardware simulation was performed in Vivado and implemented on the Basys 3 FPGA Board.

Languages

Maithili
First Language
English
Proficient (C2)
C2
Hindi
Advanced (C1)
C1

Certification

  • Verilog HDL (Udemy, Offered by Shepherd Tutorials, Online)
  • Certificate for completion of 6 months internship at Texas Instruments in DFT

Accomplishments

  • Second rank holder in M.Tech with specialization in VLSI system at NIT Tiruchirappalli.
  • Represented my school in U-17 at Nationals

Affiliations

  • Technical Head, Organising Committee, ECHO: Worked as the head of the technical team for Echo, a techno-cultural fest at UECU. My role involved organizing and managing the backend of various technical events, including quizzes, coding competitions, and literary activities
  • Esports head, sports committee, ECE society: worked as the head of esports for the ECE society at UECU. My responsibilities included organizing gaming events and managing the backend for various online games, such as Valorant, BGMI, and more.

Timeline

Digital Design Eng Intern

Texas Instruments
01.2025 - 07.2025

Master of Technology - VLSI System

National Institute of Technology

Bachelor of Technology - Electronics And Communication Engineering

Ujjain Engineering College

Class 12th - PCM

Central Public School

Class 10th -

Holy Mission High School
SUMIT KUMAR