Sunil B R

• Adaptable and proficient in learning new concepts quickly and efficiently.
• Participated in team projects, demonstrating an ability to work collaboratively and effectively.
• Worked well in a team setting, providing support and guidance
• Applied effective time management techniques to meet tight deadlines.

Client Name : Google (Aug'2023 - Till Date)

Responsibilities / Contribution :

• understanding Google's SOC FE Flow
• Understanding Realintent -Lint Tool
• Identified and analyzed critical interface bit width mismatches, open connections on SOC level and reported

Client Name : NXP semiconductor (Aug'2019-July'2023)

Responsibilities / Contribution :

• Developed complete FE Flow environment for Lint, CDC, RDC for multiple IP’s.
• Analyzed and Merged/integrated Various 3rd party IP's waivers/constraints to NXP Flow.
• Analyzed Subsystem level Lint/CDC/RDC violations , Discussed with deferent teams and worked till closure.
• Improved the Initial setup in SOC level Flat CDC Run , Reduced huge violations/noise from Toplevel .
• Analyzed SOC level CDC Violations
• Done a case study of CDC using abstract Flow , approved the same from management and driven to Implementation. Played a critical role in reducing abstract constraints noise.
• Identified spyglass cdc tool issue and filed convey the same to synopsys and filed a ticket.
• Logic synthesis on Subsystem level IPs

• Adhered to timelines to meet quality assurance targets.

Client Name: Intel

Responsibilities / Contribution :

• Responsible for developing a Memory wrapper and integrate.
• CDC and Lint analysis

Client: Thoshiba , from Wipro Technologies

Responsibilities / Contribution:

• RTL Design , Creating RTL Wrapper using Verilog for IO Libraries based on the Functional requests , Understanding the design spec. Understand the Customer Requirement.
• Creating the IO Variation Sheet
• Developed the Perl script to create RTL Wrapper based on the IO variation sheet
• Perform Lint Checks using spyglass for the same created wrapper

Passionate about learning and committed to continual improvement.

Client Name : Ineda Systems,Hyderabad

Responsibilities / Contribution:

• RTL changes/design - Design of a PLL start Controller using Verilog RTL.
• CDC, Lint analysis for the subsystems

Adhered to timelines to meet quality assurance targets.

Client : Intel

Responsibilities / Contribution:

• RTL modeling using Verilog for the functionality of GPIO/GPI/GPO Ckt., and verifying the same

Clinet : Mindtree Internal

Responsibilities / Contribution:

• Responsible for Understanding the JPEG2000 SPEC Encoder and Decoder
• Implement the same functionalities in SCI Lab and Verify