SUNILKUMAR AMBIGARA

PROJECTS

Client : NXP Semiconductors

Tool used : Cadence Virtuoso

1.VOLTA and TOBAGO(CPD generation cell) 45nm

• Time estimation of the block.
• Floor planning and Power planning.
• LVS DRC ANTENNA and MRC verifications.

2. KAVERI(CPD generation cell) 16nm

• Time estimation of the block.
• Floor planning and Power planning.
• LVS DRC ANTENNA and MRC verifications.

3. FUJI(MFIO1V8, MFIO3V3, FILCPD1V8, IREFG1V8)22FDSOI

• Time estimation of the block.
• Floor planning and Power planning.
• LVS, DRC, ANTENNA, Metal coloring and MRC verifications.
• EM, IR DROP, SHE and Metal density verification.
• Matching pattern.
• Created abstract.
• Worked on the release process of the cells.

4.IOQUA30(Test CHIP)22FDSOI

• CHIP level Floor planning and Power planning.
• LVS, DRC, COLORING, DFM and ANTENNA verification
• CHIP level tileing.
• Cleaned the Density issues at CHIP level

PROJECTS

Client : Semtech

Tool : Synopsys

1.TN3600 ( Deserializer , Mux , Frequency divider ) 7nm

• Time estimation of the overall block.
• Floor planning and Power planning.
• Extracting routing capacitor and resistor values using synopsys tool.
• LVS and DRC verification.
• Generated fill for FEOL and BEOL, instantiated at module level and verified density.

2.TN3500 ( Differential amplifier, Current mirror, LDO ) 7nm

• Time estimation of the overall block.
• Floor planning and Power planning.
• Extracting routing capacitor and resistor values using synopsys tool.
• LVS and DRC verification.

PROJECTS

Client : Texas Instruments

Tool used : Cadence Virtuoso

1.AM602 (Differential amplifier, Resistor divider, Current mirror, LDO) 45nm tsmc

• Time estimation of the block
• Floor planning, power planning.
• Matching set.
• Critical signal routing and shielding
• Local substrate isolation wherever necessary.
• LVS and DRC verification at block and module level.
• EM, ANTENNA, ESD and Metal Density verification.

INTERNAL PROJECTS

Tool : Cadence

Technology : 45nm and 180nm

1.LDO (100mA and 400mA), Differential Amplifier, Level shifter and Standard cells

2.Area estimation, Floorplanning, Stacking metals in power fet, Matching set.

3.LVS and DRC verification.

4. Understanding the shielding, EM, IR Drop, Density and ANTENNA concepts.

TRAINING

1.VLSI BASIC CONCEPTS

2.CMOS fabrication process