Suresh Krishna Tati
FPGA DESIGN ENGINEER
Mangalagiri
Summary
Dynamic FPGA, RTL, and IP Design Engineer with three years of specialized experience in RTL design, FPGA development, and IP integration using Verilog, VHDL, and SystemVerilog. Proficient in utilizing industry-standard tools such as Xilinx Vivado, Microchip Libero SoC, Lattice Radiant, and Intel Quartus Prime for comprehensive design processes, including simulation, synthesis, timing analysis, and debugging. Expertise in high-speed digital design and familiarity with AMBA protocols, SPI, I2C, UART, and DDR interfaces enhance the development of optimized FPGA architectures. Committed to delivering reliable hardware solutions tailored for complex embedded systems.
Overview
3
3
years of professional experience
Work History
FPGA Design Engineer
Inevitable Electronics Pvt Ltd
11.2024 - Current
- Resolved complex hardware–software integration issues by collaborating with cross-functional software and embedded teams, improving overall system stability, and reducing debugging time during the product lifecycle.
- Designed and implemented high-speed FPGA interfaces (SPI, UART, Ethernet, AXI, DDR), enabling reliable communication between FPGA devices and external peripherals for real-time data processing applications.
- Managed multiple FPGA design tasks simultaneously, including RTL development, simulation, synthesis, and hardware debugging, while meeting strict project deadlines, and maintaining design accuracy.
- Developed and integrated custom FPGA IP cores using Verilog/VHDL, improving system functionality, and enabling efficient data processing and hardware acceleration.
FPGA Design Engineer
Bitstar Technologies Pvt Ltd
01.2023 - 11.2024
- Designed and implemented communication and memory interfaces, including UART, I2C, SPI, DDR3, and DDR4, in FPGA-based systems using Verilog/VHDL, enabling reliable data exchange between FPGA and peripheral devices.
- Performed synthesis, place and route, and timing analysis for FPGA designs targeting Xilinx Kintex-7 devices using Xilinx Vivado 2023.2, ensuring optimized resource utilization, and timing closure.
- Managed the complete FPGA development lifecycle, including requirement analysis, RTL design, simulation, synthesis, hardware validation, and final production support.
- Developed and validated embedded FPGA-based boards, such as PFR (Programmable Flash Redundancy), using Lattice Radiant tools, ensuring stable configuration and board-level functionality.
- Improved development efficiency by creating reusable RTL modules, IP blocks, and verification components, reducing design time, and simplifying integration for future FPGA projects.
Education
B.TECH - Electrical and Electronics Engineering
Gudlavalleru Engineering College
Gudlavalleru01-2022
DIPLOMA - Electrical and Electronics Engineering
AANM & VVRSR Polytechnic College
Gudlavalleru01-2019
School of Secondary Education - SSC
ZPHS High School
Penumaka04-2016
Skills
Digital Logic Design
Embedded Systems
Linux
C Language
JTAG debugging
SOFTWARE TOOLS:
Xilinx Vivado, lattice Radient Software, Libero SOC, MATLAB, Questasim, Modelsim, EDA playground
PROJECTS
1. Embedded Electronics Modules for Multiscale Computational Cameras (EEMMCC)
Developed RTL designs and custom IP cores for Xilinx Kintex FPGA to support high-speed camera interface systems. Implemented AMBA-based communication and integrated Video-to-AXI Stream architecture for efficient data transfer and DDR buffering. Performed simulation, synthesis, and hardware validation using Xilinx Vivado with multiple functional test cases.
2. Lattice PFR (Programmable Flash Redundancy) Board Testing
Performed functional testing and validation of Lattice PFR boards using MachXO5D and CertusPro-NX FPGAs with Lattice Radiant tools. Verified board functionality across different boot modes such as JTAG, QSPI, and eMMC/SDI . Debugged hardware and FPGA configuration issues to ensure reliable system operation.
3 . VTC AI TX/RX RF Communication Subsystem
Designed and developed a VTC AI TX/RX subsystem integrating NVIDIA Jetson and Xilinx Zynq-7035 FPGA for high-speed video and RF communication. Implemented H.264 camera stream packetization on Jetson and transferred data to Zynq for processing using custom FPGA IP blocks and AXI-based architecture . Integrated RF transceivers ATMEL AT86RF215 and AD9364 for wireless transmission and reception. Utilized interfaces such as SPI, UART, Ethernet, USB, and JTAG , with development using Bare-metal and PetaLinux environments.
DECLARATION:
I hereby declare that all the information contained in this resume is in accordance with facts truths to my sense . I take full authority for the correctness of the written information.
Timeline
FPGA Design Engineer
Inevitable Electronics Pvt Ltd
11.2024 - Current
FPGA Design Engineer
Bitstar Technologies Pvt Ltd
01.2023 - 11.2024
DIPLOMA - Electrical and Electronics Engineering
AANM & VVRSR Polytechnic College
B.TECH - Electrical and Electronics Engineering
Gudlavalleru Engineering College
School of Secondary Education - SSC
ZPHS High School