Sureshkumar Kuna

Project1: RIVOS

Technology Node: 7nm

Role: Lead Engineer

Level:Block Level

Duration: Dec’ 2023 – till date

Tasks: Leading a team, Synthesis, LEC, Floor planning, Placement, Clock tree synthesis, Routing, DRC & LVS

Roles & Responsibilities:

• Responsible for leading the team of 10 members meeting the deliverables and a block – level implementation from RTL – GDSII activities.
• Handled 1 blocks with 568 macros and 0.2M gate count and 896MHz frequency with 3 Clocks and 15 Metal layers.
• Carried out Floorplan iterations to address the density and congestion issues.
• Worked on Tool based congestion reduction methods in placement stage.
• Worked on Subsystem level Timing.
• Worked on ECO cycles to fix timing violations.

Project1 : Description: Responsibilities: Project2 : Description: Responsibilities: Project3: Description: Responsibilities: Project4: Description: Responsibilities:

Block1: smu_mpdma_tf_t

• Operating Frequency: 1.54Ghz
• Instance Count: 1.52M
• Macros: 93
• Tools: Synopsys ICC2, primetime, Star-RC/XT

Block2: smu_clkc_t

• Technology used: 6nm,
• Operating Frequency: 1.6Ghz
• Instance Count: 90K

Block3: smu_twix_iod_t

• Technology used: 6nm,
• Operating Frequency: 1.6Ghz
• Instance Count: 75K

Block4: smu_asp_t

• Technology used: 6nm,
• Operating Frequency: 2.1Ghz
• Instance Count: 210K
• Duration: A0 : Feb2022 - Sep’2022

B0: Oct’2020- Jan’ 2023

C0: Jan’ 2023 - Sep’ 2023

• Netlist Checks & SDC Sanity Check.
• Floor Planing is based on technology specific guidelines and data flow diagram.
• Placement & Initial Congestion Analysis.
• Block level & Interface timing closure.
• Caliber violations closure based on SubFC reports.

Block1: Memory controller partition

• Operating Frequency: 1.6Ghz
• Instance Count: 1.37M
• Macros: 71
• Multi Voltage partition.
• Tools: Synopsys ICC2, primetime, Star-RC/XT, VCS Compiler, LEC, Ansys Redhawk.
• Duration: A0 : Oct’2019 – Sep’2020

B0 : Oct’2020- May’ 2021

C0 : Jun’ 2021 - Jan’ 2022

Block2: Infra partition

• Technology used: 10nm, sdg74 process, Intel Foundry
• Operating Frequency: 1.6Ghz
• Instance Count: 295k
• Multi Voltage partition.
• Netlist Checks & SDC Sanity Check.
• Floorplaning based on the technology specific guidelines and data flow diagram.
• Placement & Initial Congestion Analysis.
• Block level & Interface timing closure.
• Partition level VCLP & FEV cleanup.
• Caliber violations closure based on SubFC reports.
• RV cleanup of the partitions (PDN fixes).
• Voltage area and PG region creation
• Blocks: rap_mmu
• Technology: 16nm, TSMC foundry
• Instance Count: 1M
• Operating Frequency:1GHZ
• Duration: jun ’2019 – Aug’2019
• Make flow setup for the blocks.
• Performed complete physical design activity starting from floor planning, placement, CTS and routing
• Post-Placement Timing Quality Check. Clock tree Synthesis and Routing.
• Signoff Route DRC & LVS.
• Extraction, STA and ECOs Implementation
• Blocks: gc_ge2_dist_t
• Technology: 7nm,
• Instance Count: 14k
• Operating Frequency: 1.8Ghz
• Macro Count: 6
• Duration: April’2018 – May’2019
• Netlist Checks & SDC Sanity Check.
• Floorplaning based on the technology specific guidelines and data flow diagram.
• Placement & Initial Congestion Analysis.
• Block level & Interface timing closure.
• Partition level VCLP & FEV cleanup.
• Caliber violations closure based on SubFC reports.
• RV cleanup of the partitions (PDN fixes).
• Voltage area and PG region creation.