Summary
Overview
Work History
Education
Skills
Certification
Contact
Timeline
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Sureshkumar Kuna

Sureshkumar Kuna

Bengalore

Summary

Experienced Physical Design Engineer in the VLSI field with over 7.8 years of dedicated expertise. Proficient in all facet of the ASIC design cycle, exhibiting superior performance at key phases including Place & Route, timing signoff, IR, LEC, and DRC resolution. Motivated to stretch myself, learn new things, use my experience and expertise to significantly excel and contribute to the organizational growth trajectory.

Overview

8
8
years of professional experience
1
1
Certification

Work History

Technical Lead

Quest-Global
Bengaluru
07.2024 - Current
  • Project 1: AMD ODC
  • Technology Node: 3nm,
  • Role: Lead Engineer
  • Duration: Aug 2024 – present
  • Tasks : include leading a team, synthesis, LEC, floor planning, placement, clock tree synthesis, routing, DRC, and LVS.

Lead Engineer

Proxelera
Bengaluru, India
10.2023 - 07.2024

Project1: RIVOS

Technology Node: 7nm

Role: Lead Engineer

Level:Block Level

Duration: Dec’ 2023 – till date

Tasks: Leading a team, Synthesis, LEC, Floor planning, Placement, Clock tree synthesis, Routing, DRC & LVS

Design Engineer II

Adeptchips Services
Bengaluru, India
06.2017 - 10.2023


Project1: Brighthorn (AMD)

  • Operating Frequency: 1.54Ghz
  • Instance Count: 1.52M
  • Macros: 93
  • Tools: Synopsys ICC2, primetime, Star-RC/XT
  • Duration: A0 : Feb2022 - Sep’2022

B0: Oct’2020- Jan’ 2023

C0: Jan’ 2023 - Sep’ 2023

Project2: PVC (intel)

  • Operating Frequency: 1.6Ghz
  • Instance Count: 1.37M
  • Macros: 71
  • Tools: Synopsys ICC2, primetime, Star-RC/XT, VCS Compiler, LEC, Ansys Redhawk.
  • Technology used: 10nm, sdg74 process, Intel Foundry
  • Duration: A0 : Oct’2019 – Sep’2020

B0 : Oct’2020- May’ 2021

C0 : Jun’ 2021 - Jan’ 2022

Project3: SOC (AlphaIcs)

  • Technology: 16nm, TSMC foundry
  • Instance Count: 1M
  • Operating Frequency:1GHZ
  • Duration: jun ’2019 – Aug’2019

Project4: AMD ODC

  • Blocks: gc_ge2_dist_t
  • Technology: 7nm,
  • Instance Count: 14k
  • Operating Frequency: 1.8Ghz
  • Macro Count: 6
  • Duration: April’2018 – May’2019

Responsibilities:

  • Netlist Checks & SDC Sanity Check, Floorplaning based on the technology specific guidelines and data flow diagram, Placement & Initial Congestion Analysis , Block level & Interface timing closure, Partition level VCLP & FEV cleanup, Caliber violations closure based on SubFC reports , Voltage area and PG region creation, Meeting the latency requirement to be aligned with subFC Timing requirements, Clock pull/Push for Interface timing closure, Implementation of low power Methodology in the design. Resolving the Multi voltage violations, Enhancing the power grid for RV closure, Optimizing the DRC count at the congested hotspot,


  • Custom clock tree implementation to meet the FCT Clock Spec, Optimizing the DRC count at the congested hotspot, Analog routes created manually from TOP level requirement, Skew reduction using clock balancing and skew groups, Anchor buffers created for high fanout and clock balancing, Applied NDR’s using cts_skip_track and shielding for reducing high aggressive nets.

Education

Master of Science - Microelectronics

Bits-Pilani
Bengaluru
12-2024

Bachelor of Science - Electronics And Communications Engineering

JNTUK
Andhra Pradesh
2016

High School Diploma -

State Board Technical Education
Andhra Pradesh
2013

Skills

  • P>Place and Route : Cadence Innovus, SoC Encounter, Synopsys ICC2 Synopsys PrimeTime Cadence Tempus Experience in TCL /TK Programming Tweaker Conformal(LEC) Synopsys Fusion Compiler PERL Scripting Microsoft Powerpoint Microsoft Office Microsoft Excel
  • P>Interpersonal Skills Organizational and planning skills Good listener and communicator Time Management: Demonstrated leadership skills and a team player

Certification

Received WOW - Individual Excellence Award from Aricent for dedication and focused effort on Navi 12 project which helped the smooth execution of the Navi12 Program. Received the Star Performance Certificate from AdeptChips for outstanding contribution and meritorious effort while executing as a PD Engineer.

Contact

Jai Royal Park, Bengalore, India 560048

Timeline

Technical Lead

Quest-Global
07.2024 - Current

Lead Engineer

Proxelera
10.2023 - 07.2024

Design Engineer II

Adeptchips Services
06.2017 - 10.2023

Master of Science - Microelectronics

Bits-Pilani

Bachelor of Science - Electronics And Communications Engineering

JNTUK

High School Diploma -

State Board Technical Education
Sureshkumar Kuna