Experienced Physical Design Engineer in the VLSI field with over 7.8 years of dedicated expertise. Proficient in all facet of the ASIC design cycle, exhibiting superior performance at key phases including Place & Route, timing signoff, IR, LEC, and DRC resolution. Motivated to stretch myself, learn new things, use my experience and expertise to significantly excel and contribute to the organizational growth trajectory.
Project1: RIVOS
Technology Node: 7nm
Role: Lead Engineer
Level:Block Level
Duration: Dec’ 2023 – till date
Tasks: Leading a team, Synthesis, LEC, Floor planning, Placement, Clock tree synthesis, Routing, DRC & LVS
Project1: Brighthorn (AMD)
B0: Oct’2020- Jan’ 2023
C0: Jan’ 2023 - Sep’ 2023
Project2: PVC (intel)
B0 : Oct’2020- May’ 2021
C0 : Jun’ 2021 - Jan’ 2022
Project3: SOC (AlphaIcs)
Project4: AMD ODC
Responsibilities:
Received WOW - Individual Excellence Award from Aricent for dedication and focused effort on Navi 12 project which helped the smooth execution of the Navi12 Program. Received the Star Performance Certificate from AdeptChips for outstanding contribution and meritorious effort while executing as a PD Engineer.
Jai Royal Park, Bengalore, India 560048