Suruchi
Bengaluru
Summary
PDK/CDK Engineer with 3+ years of experience at Texas Instruments, developing design enablement solutions and automation utilities for analog and digital technology nodes (28nm, 45nm, 65nm). Expert in SKILL and Python scripting for PDK component development, logic expression validation, and multi-release QA frameworks. Known for delivering impactful automation tools, including a DVCon 2024-featured dummy fill generator, that accelerates physical verification and improves quality.
Overview
3
3
years of professional experience
1
1
Certification
Work History
PDK/CDK Engineer
Texas Instruments
Bengaluru
07.2022 - Current
- Designed and delivered 90+ parameterized cells (pcells) in Cadence Virtuoso for 28nm, 45nm, and 65nm analog and digital nodes.
- Developed a dummy fill generator using SKILL and Python to automate metal fill DRC and instantiation workflows; selected for DVCon 2024.
- Created a Python-based Asset vs DRC Logic Expression Comparator, parsing logic trees to flag mismatches.
- Built a Layer Logic Comparator for detecting layer expression-level differences across DRM-DRC versions.
- Developed and enhanced multiRelease QC framework with logic validation, reducing regression cycles by 60%.
- Developed rule deck encryption utility to ensure secure process file distribution.
- Collaborated with process engineers to optimize CDK components and ensure DRC/LVS compliance.
- Implemented automated test suites for layout view and PDK QA across releases.
Education
M.Tech - VLSI & Embedded Systems
DTU (Delhi Technological University)
India01.2022
B.Tech - Electronics And Communications Engineering
ABES Engineering College
India01.2017
Skills
Languages: Python, SKILL, Verilog, C/C
Tools: Cadence Virtuoso, PVS, Assura, Xilinx Vivado, LTSpice, GIT
Domains: PDK/CDK Development, DRC/LVS, PDK QA
Technology Nodes: 28nm, 45nm, 65nm (analog/digital process nodes)
Platforms: Linux, Windows, Mac
Certification
- Crash Course on Python – Coursera
- Hardware Modeling Using Verilog – NPTEL
- Embedded System Design – Multisoft Systems
Academic Projects
OTRA-based MISO shadow filter design (master's final year thesis), LTSpice, 180nm CMOS, designed and simulated a MISO (multiple-input single-output) shadow filter using an operational transresistance amplifier (OTRA) to implement electronically tunable low-pass, band-pass, high-pass, and notch filters, eliminated the need for resistors and summing amplifiers, enabling full IC integration
Design and implementation of Newton-Raphson divider using Wallace and Karatsuba multipliers, Xilinx Vivado, explored high-speed divider architecture optimized with Wallace and Karatsuba multipliers to evaluate performance, convergence speed, and area
Implementation of UART and I2C protocols, Xilinx Vivado, implemented UART and I2C protocols in an FPGA for serial communication between embedded devices
Vehicle tracking system (B.Tech project), Atmel Studio, Proteus, built a GPS and GSM enabled vehicle tracking system using ATmega microcontroller, enabling real time location updates via SMS
Timeline
PDK/CDK Engineer
Texas Instruments
07.2022 - Current
M.Tech - VLSI & Embedded Systems
DTU (Delhi Technological University)
B.Tech - Electronics And Communications Engineering
ABES Engineering College
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