Summary
Overview
Work History
Education
Skills
Awards
Additional Information
Hobbies and Interests
Languages
Timeline
Generic

SUSHEEL KUMAR MAHINDERKER

Bengaluru,KA

Summary

Dynamic Senior Firmware Engineer with over 7 years of specialized experience in SoC power management, firmware development, and silicon debug at Intel. Expertise in reset flows, idle/active power management, overclocking, and debug infrastructure drives significant improvements in power efficiency while enhancing user experiences in next-generation client SoCs. Proven hands-on proficiency in firmware design, development, unit testing, and validation using Embedded C, C++, and Python, consistently adhering to rigorous quality and coding standards. A strong foundation in system-level optimization and cross-team collaboration complements advanced problem-solving skills and an expanding knowledge base in machine learning.

Overview

8
8
years of professional experience

Work History

Senior Firmware Engineer

Intel Corporation
01.2018 - Current

Firmware Development & Debug:

Designed, developed, unit-tested, and debugged Power Management (PM) firmware features for Intel Client SoCs, contributing directly to longer battery life and improved system performance.

Power Management Expertise:

  • Idle PM: Implemented PKGC states, Compute Die C-states, Core C-states, and Save/Restore features for Intel’s SoCs.
  • Active PM: Delivered Overclocking, Workpoint, and Power Delivery features ensuring competitive power-performance balance.
  • Interfaces & Debug: Worked on Mailboxes, Telemetry, and Crashlog features.

Silicon Debug:

  • Pre-Silicon: Analyzed and resolved firmware issues by debugging at cluster level trackers and simulations.
  • Post-Silicon: Enabled critical firmware feature bring-up during first power-on, developed debug patches & workarounds for hardware bugs, and contributed in taskforces for time-critical issue resolution.

Global Collaboration:

Served as part of Manual Debug Team (MDT), including a 6-month onsite assignment in Hillsboro, Oregon (USA) and Successfully contributed to Intel’s Oregon (USA) Power-On lab for critical silicon bring-up, ensuring competitive power-performance solutions on Meteor Lake and other Intel's soc platforms.

Tools & Programming:

Strong experience in C/C++, Python, Linux environment, and Git. Worked with internal debug tools like Power Trace & Python SV Debug Tool for trace analysis.

Software Practices:

Coding guidelines, Quality norms, Unit Test Development

Additional Knowledge:

Machine Learning fundamentals

Collaboration:

Partnered with cross-functional teams during system bring-up, including onsite (US assignment) and offshore debug. Actively contributed to taskforces under time-critical conditions, accelerating resolution of critical HW/FW issues.

Education

Master of Technology (M.Tech.) - Computer Science Engineering

VIT University
Vellore, Tamil Nadu
01.2018

Bachelor of Technology (B.Tech.) - Computer Science Engineering

RGIT
01.2015

Skills

    Firmware Development & Engineering

    Design and development of embedded firmware solutions

    Comprehensive unit testing and validation methodologies

    Static code analysis and quality assurance

    Pre-silicon and post-silicon debugging expertise

    Firmware architecture design and implementation

    Power Management Specialization

    Reset flows design and implementation

    Idle Power Management: Compute Die C-states, PKGC states, Core C-states, P-states

    Save/Restore feature development and optimization

    Active Power Management: Workpoint optimization, Power Delivery solutions

    Overclocking flows and performance tuning

    SoC Power Management Architecture expertise

    Idle/Active State Management strategies

    Debug & Analysis Tools

    Power Trace analysis and optimization

    Python SV Debug Tool proficiency

    Telemetry systems implementation and monitoring

    Crashlog analysis and debugging

    Cluster-level tracker analysis and resolution

    Advanced debug/trace tools utilization

    Programming Languages & Scripting

    Embedded C programming

    C development

    Assembly language programming

    Python scripting and automation

    MATLAB scripting and analysis

    Development Tools & Platforms

    Git version control and collaboration

    Linux development environment

    Integrated debug and trace tools

    Silicon bring-up platforms and methodologies

    Software Engineering Practices

    Adherence to coding guidelines and standards

    Quality norms implementation and compliance

    Unit test development and automation

    Code review and validation processes

    Documentation and technical specifications

    System Architecture & Knowledge

    SoC Power Management Architecture design

    Silicon bring-up procedures and methodologies

    Hardware-firmware integration expertise

    System-level optimization strategies

    Additional Technical Competencies

    Machine Learning fundamentals and applications

    Cross-platform development experience

    Performance analysis and optimization

    Collaboration & Leadership

    Cross-functional team partnership and coordination

    International collaboration (onsite US assignment experience)

    Offshore development and debug coordination

    Taskforce leadership under time-critical conditions

    Critical hardware/firmware issue resolution acceleration

    Stakeholder management and technical communication

Awards

DEG Group Recognition Award (GRA): High-quality contributions to successful bring-up of Intel’s first 1278 silicon on Arrow Lake.

IVE Division Recognition Award (DRA): Collaborated across teams to resolve 13 critical timing gate issues, enabling early production TI of ARL816 C-die.

CPV Division Recognition Award (DRA): Resolved 20+ critical overclocking issues across iVE, CCG SIV, Design, and FW teams, enabling high-quality ARL-S silicon validation.

CEG Division Recognition Award (DRA): Recognized for “All Hands on Deck” execution to enable Arrow Lake-S A0 silicon power-on.

CVI Division Recognition Award (DRA): Enabled ARL-S Windows OS boot in hybrid core configuration by overcoming X-Propagation issues.

MTL Division Recognition Award (DRA): Delivered timely, production-quality PM firmware releases (ES1/Alpha) to external customers.

Additional Information

Work Authorization: L1B Visa (Intel Corporation) | Valid : 2025 - 2028

Hobbies and Interests

Chess, Cricket

Languages

English
Hindi
Kannada
Marathi
Telugu

Timeline

Senior Firmware Engineer

Intel Corporation
01.2018 - Current

Bachelor of Technology (B.Tech.) - Computer Science Engineering

RGIT

Master of Technology (M.Tech.) - Computer Science Engineering

VIT University
SUSHEEL KUMAR MAHINDERKER