Dynamic Staff Engineer with extensive experience at QUALCOMM India, adept at leading complex physical verification projects and mentoring teams. Proven ability to develop innovative engineering solutions and manage multiple subsystems. Expertise in physical verification flows and a strong problem-solving mindset, successfully delivering projects on time while enhancing operational efficiency.
10+ years of experience in Physical Verification Domain
Currently leading a project for complete PV Signoff.
Have worked on 20+ Projects with tech nodes ( 4nm/5nm/7nm/10nm/11nm/14nm/28nm)
Have practical knowledge in TSMC and Samsung foundry rules and checks
Proficient in using Synopsys ICC2/FC, Cadence Innovus, Mentor Graphics Calibre tools to drive signoff activities
Have experience in interacting with PD/PDN/STA/SOC-PV/RDL teams, CAD/IP/MEM/STDCELL teams and Management to achieve smooth closure of projects
Have worked on multi hierarchy subsystems and hard macros
Overview
9
9
years of professional experience
Work History
Staff Engineer
QUALCOMM India Private Limited
BENGALURU
02.2016 - Current
Analyzing PV reports of HM’s in each stages of PD to maintain good health.
Reviewing critical block with respect to Timing for Cell/Route congestion issues, guiding PD on workarounds to derisk them
Lead 2 small projects for PV activities
Quranium_r2 : TSMC 7FF
SMSM : Leading signoff PV activities for QTI blocks of sf3p tech
Worked on block level Floorplanning for some of blocks in AURORA, NETRANI and Pakala.
SOC-FP non-FT tasks like lib_prep, build DB, partitioning, IP/MACRO/PAD placement in HALLIDAY
Worked on ECO-implementation for one of block in Waipi for signoff, leakage, GLS, GKC-scan trace, TDRC runs, reviews and fixes
Being part of FP, NRE and duration reduction, owned FP implementation along with signoff for multiple blocks in Project Aurora. Successfully completed P3-FP activity within targeting time.
Worked on SOC Preroute designing and closure for CLARENCE, along with SOC-Netlist checks for same project
Involved in Matrix, SOC Floor planning activities like Preparing Build DB from DC netlist, PadRing Closure, IO reviews and placements wrt Timing/RDL/Partition,FT data preparation with preplacing the logic, inst grouping, fence creation, FT insertion, Pin placement, CXO network coverage, FV/CLP fixes on FT inserted netlist, LEFvsLEF checks on partitions
Synopsys : ICV tool validation for PV
As part of Methodology, wrote many scripts to reduce manual fixing/review effort
Currently leadinga project for PV with more than 120 blocks and owned one subsystem.
Education
B.E in Electronics And Communications -
PESITM
Shivamogga, Karnataka
08-2013
Skills
Ability to work Independent and develop quick engineering solutions for complex problems
High problem-solving capacity and good tolerance for ambiguity, able to prioritize tasks
Excellent understanding and hands on experience in Physical Verification flows
Capability of handling multiple blocks/Sub-systems for PV