Tanvi Agrawal
Bangalore
Summary
As an experienced ASIC Digital Design Engineer, I possess
expertise in DDR5, DDR4, Testchip, BIST, DFI, LINT/CDC. My technical skills are also vast and cover a broad range of competencies. I have done M.Tech. in Embedded System from NIT Jaipur, B.E. in Electronics and Communication from KIET Ghaziabad. I am also professional in relevant skills and have completed several training programs.
Overview
2
2
years of professional experience
Work History
ASIC Design Engineer
Synopsys india Ltd
01.2022 - Current
- Cooperated with systems, hardware and software engineers as well as program management to design products meeting market needs.
- Working on design verification of Synopsys' most recent memory PHY IP products. These support numerous DIMM configurations including UDIMM, RDIMM, and LRDIMM and cater to various DDR standards.
- Responsible to perform LINT/CDC/RDC check thorough spyglass and vcspyglass tools to improve the RTL design quality.
Education
M.Tech - Embedded System
Malaviya National Institute of Technology
Jaipur07.2021
B.Tech - Electronics And Communications
KIET Group of Institutions
Ghaziabad06.2018
Skills
- Verilog
- System Verilog
- LINT/CDC
- Verdi
- Shell Scripting
Technical Skills
- Hands on experience in LINT/CDC checks and shell scripting.
- Possess knowledge of multiple protocols (DDR, DFI, BIST, Testchip).
- Experience with Spyglass tool, VCSpyglass tool & Verdi.
Internships
- Technical Intern - Synopsys India Pvt. Ltd Bengaluru, Karnataka
Worked in DDR PHY IP RTL Design team.
Duration: - Jan '22 - Sep '22 - Part time intern - BHARAT ELECTRONICS LIMITED,
Sahibabad, U.P.
Duration: - June '17 - July '17
Projects
- Spyglass Power Analysis for finding power loopholes at an Early-
Stage RTL. - VCSPYGLASS setup for CDC/LINT/RDC checks.
- BIST Controller RTL enhancements and quality checks, based on
customer requirement. - Testchip quality checks, based on customer requirement.
Accomplishments
- Paper titled "Early Stage Power Estimation and Exploration" selected in Global Semiconductor Alliance(GSA) Women's Leadership Initiative 2022 WISH Conference.
- Received Spontaneous Recognition Award from Synopsys for performing the CDC checks, Smarter team work skills, Passion, Execution Excellence and Integrity.
Timeline
ASIC Design Engineer
Synopsys india Ltd
01.2022 - Current
M.Tech - Embedded System
Malaviya National Institute of Technology
B.Tech - Electronics And Communications
KIET Group of Institutions
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