Tapsir Shaikh
Bangalore
Summary
Skilled Digital Design Engineer with extensive experience at Texas Instruments, focusing on SoC constraint methodologies and achieving timing closure for automotive and robotics MCUs. Proficient in STA tools, including Tempus and Genus for synthesis, along with strong TCL and Shell scripting capabilities. Demonstrated success in automating quality control checks and mentoring junior team members, enhancing team productivity and project outcomes. Seeking to leverage expertise to drive innovations in digital design engineering.
Overview
9
9
years of professional experience
Work History
Digital Designer Engineer
Texas Instruments
Bangalore
12.2020 - Current
- Developed SoC constraint methodologies for a range of automotive and robotics MCUs.
- Directed overall constraint development and ensured timing closure for different I/O interface IPs, namely SPI, QSPI, OSPI, Ethernet, I2S, etc.
- Updated interface I/O timing numbers in the product datasheet.
- Ensured accuracy and finalization of derates, uncertainty, and design margins in STA closure.
- Executed timing signoff and elevated design phase by developing SOC level constraints.
- Developed multiple scripts to automate various QC checks for quality signoff, guiding freshers in the team.
Digital Design Engineer II
Open Silicon
Pune
02.2018 - 11.2020
- Worked on multiple interconnect IPs, including USB3 and SATA.
- Implemented constraints, delivery, and validation for all the modes.
- Delivered RTL feedback to designer regarding timing paths.
- Handled ETM generations, LEC cleanup, synthesis power estimation runs, and STA glitch analysis.
- Delivered essential input on CTS and placement issues throughout the design process.
- Employed TSO and manual techniques to ensure timely design completion.
Digital Design Engineer I
Seagate Technologies
Pune
01.2016 - 02.2018
- Completed a Physical Design Internship for 6 months.
- Started working on shift and capture mode test mode timing analysis, check timing cleanup, and ECO generation for flat SOC.
Education
M.Sc. - Electronics
Pune University
Pune01.2016
B.Sc. - Electronics
RYK college of Science
Nashik01.2014
HSC -
Bhonsala Military College
Nashik01.2011
SSC -
Pravara Public School
Rahata01.2009
Skills
- STA: Tempus, Primetime, Innovus
- Synthesis: Genus
- LEC: Conformal
- Power: Voltus
Publications
Quick and Efficient Extraction of Library Pessimism: Enabler for Faster Hold Timing Closure, Design Automation Conference (DAC)
Hobbies and Interests
- Engaged in various sports activities
- Pet Lover
- Trekking, Outdoor Adventure Skills
Languages
- Fluent in English, Hindi, and Marathi
Personal Information
- Date of Birth: 05/08/93
- Gender: Male
Disclaimer
I declare that the information provided is accurate to the best of my knowledge
Timeline
Digital Designer Engineer
Texas Instruments
12.2020 - Current
Digital Design Engineer II
Open Silicon
02.2018 - 11.2020
Digital Design Engineer I
Seagate Technologies
01.2016 - 02.2018
M.Sc. - Electronics
Pune University
B.Sc. - Electronics
RYK college of Science
HSC -
Bhonsala Military College
SSC -
Pravara Public School
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