Thakur Singh Maroo
Noida
Summary
Dynamic professional with extensive experience in layout design and product validation. Skilled in DRC, LVS, EMIR and product validation processes. Recognized consistently for performance excellence and contributions to success in VLSI industry.
Overview
14
14
years of professional experience
Work History
Principal Product Validation Engineer
Cadence Design Systems
Noida
02.2023 - Current
Led validation efforts for layout migration tools and Virtuoso L-XL core functionalities.
Created customer test layouts to support TSMC, Samsung, and Intel foundries' validation needs.
Validated Virtuoso across PDKs to benchmark next-generation solutions and enhance tool performance.
Facilitated adoption of innovative layout technologies, enhancing design processes and tool effectiveness.
Led a team of 5 to implement work practices that increased automation and streamlined validation workflows.
Staff Layout Engineer
Insemi Technologies
Bengaluru
12.2018 - 02.2023
Client – AMD
• Summary: In my 3+ years of Layout work at AMD mainly I have worked on Cache memory (L1, L2 and L3), standard cell and clock macros. I have worked on -
• Foundry: TSMC N7, N6, N5 and N3.
• L1 Memory work in N3: Designing major block and top-level verification.
• Serdes digital block: Layout and verification in 2 months in TSMC-N5 tech.
• DFS 8phase: Worked on design changes, electrical fixes of macro.
• N6 standard cells: Ported N7 stdcells using Skill script and improve timing of those cells.
• Automation: Ported stdcells from one format to another format in N3.
AMS Layout Engineer II
Synopsys
Noida
05.2016 - 08.2018
• Summary: In 2 years of work in Synopsys I have worked on Memory compiler, worked on major blocks of memory - Decoder, Local control, Local IO, global control and other optional cells of compiler.
• Foundry: Intel10nm, Intel22nm, Samsung 8nm, TSMC 7nm
• Memory verification – Worked on DRC, LVS, DFM, ERC, EM-IR.
• Milestone: Delivered test chip in 35 days for N7+ HPC compiler.
Automation: Created script which auto-runs drc and lvs and perl wrapper which will run verification on specified options of compiler.
Senior Layout Engineer
Sankalp Semiconductor
Noida, Bengaluru
08.2012 - 05.2016
Client – ARM
• Summary: In ARM I started memory layout work, Learned all the aspects of memory compiler design and verification - Layout, schematic, DRC, LVS, DFM, LFD, ERC, LVL, tiling, Instance level verification etc.
• Milestone: Timely delivered all the project with tight schedule and last moment design changes.
• Automation: Created small useful scripts - e.g., Replacing a layer in all cells of the compiler.
Education
PG Diploma - VLSI
RV VLSI Design Centre
Bengaluru04-2012
Bachelor of Technology - Electronics And Communications Engineering - 61%
Geetaanjali Institute of Technical Studies
Udaipur04-2011
Skills
- Layout design
- DRC, LVS and EMIR
- Layout Migration
- Product Validation(Virtuoso)
- Perl, SHELL, SKILL scripting
- Advance Nodes
- Tools - Virtuoso, Custom compiler, Calibre, Pegasus, Totem, VS code
Accomplishments
Catalyst Award (2026) – Recognized at Cadence for driving multiple urgent MTK ALM deliverables with exceptional ownership and execution.
GEM Award (2021) – Honored at AMD for significant contributions to the TSMC N3 technology program, demonstrating technical leadership and impactful collaboration.
Outstanding Delivery Award (2018) – Commended at Synopsys for the timely and successful delivery of the SMIC test chip within a challenging 35‑day schedule, while managing evolving customer requirements.
Project Excellence Award (2018) – Awarded at Synopsys for key contributions to the Intel 10nm project, ensuring high‑quality deliverables under stringent timelines.
Key Contributor Recognition (2015) – Recognized at ARM for dedicated and impactful contributions to the GF14LPP project, playing a vital role in project execution and success.
GEM Award (2021) – Honored at AMD for significant contributions to the TSMC N3 technology program, demonstrating technical leadership and impactful collaboration.
Outstanding Delivery Award (2018) – Commended at Synopsys for the timely and successful delivery of the SMIC test chip within a challenging 35‑day schedule, while managing evolving customer requirements.
Project Excellence Award (2018) – Awarded at Synopsys for key contributions to the Intel 10nm project, ensuring high‑quality deliverables under stringent timelines.
Key Contributor Recognition (2015) – Recognized at ARM for dedicated and impactful contributions to the GF14LPP project, playing a vital role in project execution and success.
Timeline
Principal Product Validation Engineer
Cadence Design Systems
02.2023 - Current
Staff Layout Engineer
Insemi Technologies
12.2018 - 02.2023
AMS Layout Engineer II
Synopsys
05.2016 - 08.2018
Senior Layout Engineer
Sankalp Semiconductor
08.2012 - 05.2016
PG Diploma - VLSI
RV VLSI Design Centre
Bachelor of Technology - Electronics And Communications Engineering - 61%
Geetaanjali Institute of Technical Studies