Thiraviyam Bagavathiraja
Bangalore
Summary
Results-driven Design Verification Engineer with over six years of experience at Maxvy Technologies. Expert in UVM and System Verilog, successfully implementing coverage-driven verification and protocol compliance. Proven problem solver, enhancing testbench environments and achieving significant improvements in design validation efficiency. Adept at collaborating with cross-functional teams to deliver high-quality results.
Overview
7
7
years of professional experience
Work History
Design Verification Engineer
Client(Sandisk)
Bangalore
09.2024 - Current
- Integrated verification testbench environment to validate design functionality and performance.
- Executed test cases for thorough validation of design specifications.
- Analyzed test results to identify design flaws and inconsistencies.
- Implemented directed and constrained random tests using SystemVerilog constructs.
- Developed SystemVerilog testbench to ensure compliance with SCA protocol.
- Signed off on validation activities for internal and external customer releases.
Design Verification Engineer
Client (Infinera India Pvt Ltd)
Bangalore
07.2021 - 03.2023
- Integrated I2C, UART, SPI, and QSFP environments, establishing a basic testbench setup.
- Developed comprehensive test plans and wrote test cases aligned with FPGA documentation.
- Executed RTL regression, debugging failures and tracking corresponding JIRA issues.
- Performed code coverage analysis on multiple FPGA blocks to ensure functionality.
- Created internal documentation to enhance team understanding of project tasks.
- Conducted training sessions for newcomers on System Verilog and UVM methodologies.
Verification Engineer
Bangalore
Bangalore
07.2020 - 07.2021
- Analyzed MIPI CSI-2 specifications to ensure compliance with protocol requirements.
- Collaborated on C-PHY layer protocol development for physical layer applications.
- Designed verification environment for C-PHY, supporting both transmitter and receiver functionalities.
- Engineered mapper, demapper, serializer, and deserializer blocks for effective C-PHY data handling.
- Implemented low-power (LP) mode operations for optimized C-PHY transmission and reception.
Verification Engineer
Bangalore
Bangalore
04.2019 - 06.2020
- Comprehended I3C and PMIC specifications to ensure alignment with project requirements.
- Updated test plan and authored test cases in accordance with JEDEC specifications.
- Executed RTL regression tests, debugging failures and addressing corresponding JIRA issues.
- Analyzed and enhanced code coverage, ensuring thorough functional testing.
Design Verification Engineer
Maxvy Technologies Private Limited
Bangalore
04.2019 - Current
- Served as Design Verification Engineer at Maxvy Technologies since April 2019.
- Accumulated over six years of extensive experience in design verification.
- Demonstrated strong programming proficiency in Verilog and System Verilog.
- Applied advanced verification techniques using UVM, Code Coverage, Functional Coverage, and Assertions.
- Gained 1.6 years of experience in PCB design to support verification processes.
Education
B.E. - Electronics and Communication
PET Engineering College
Vallioor, Tamilnadu01.2016
HSC - Cheranmahadevi, Tamilnadu
Sivanthi Matriculation Higher Secondary School
Cheranmahadevi, Tamilnadu01.2012
SSC - Cheranmahadevi, Tamilnadu
Sivanthi Matriculation Higher Secondary School
Cheranmahadevi, Tamilnadu01.2010
Skills
- UVM verification and testbench development
- RTL regression and code coverage
- Protocol compliance and functional coverage
- Problem solving and verification planning
- Coverage-driven verification and constraint random testing
- IP verification
Eda Tools
- Cadence – Xcelium
- Synopsis VCS
- GTKwave
Other Roles Responsibilities
Handled team of 2 members
Disclaimer
I do hereby declare that the above information is true to the best of my knowledge.
Timeline
Design Verification Engineer
Client(Sandisk)
09.2024 - Current
Design Verification Engineer
Client (Infinera India Pvt Ltd)
07.2021 - 03.2023
Verification Engineer
Bangalore
07.2020 - 07.2021
Verification Engineer
Bangalore
04.2019 - 06.2020
Design Verification Engineer
Maxvy Technologies Private Limited
04.2019 - Current
B.E. - Electronics and Communication
PET Engineering College
HSC - Cheranmahadevi, Tamilnadu
Sivanthi Matriculation Higher Secondary School
SSC - Cheranmahadevi, Tamilnadu
Sivanthi Matriculation Higher Secondary School
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