Summary
Overview
Work History
Education
Skills
Leadership Experience
Toolsused
Projects
Scriptinglanguages
Training
Interests
Timeline
Generic
THOUSIF SHAIK

THOUSIF SHAIK

VLSI PHYSICAL DESIG ENGINEER
Ponnur

Summary

  • Experienced VLSI Physical Design Engineer with over 3.2 years of expertise in defining and optimizing block-level floorplans, managing macro placement. Proficient in executing standard cell placement and routing (PnR) using Synopsys ICC2, with a strong focus on optimizing congestion and wire lengths for timing closure. Demonstrated ability in post-routing cleanup, ensuring designs are LVS clean and free of violations.
  • Adept at conducting DRC and LVS checks using Calibre and IC Validator, with a deep understanding of rule decks from leading foundries such as TSMC, GF, Intel, and UMC. Played a pivotal role in implementing Physical Verification (PV) flows at the block level and resolving antenna violations. Experienced in addressing power IR drop issues through strategic techniques like defining keep-outs and swapping cells, supported by comprehensive analysis using Redhawk.
  • Proficient in generating SPEFs for use in Static Timing Analysis (STA) and performing STA with Synopsys PrimeTime to achieve timing closure across all PVT corners. Knowledge in eveloping and maintaining TCL scripts to automate physical design tasks, enhancing productivity and resolving Design Rule Violations (DRVs) efficiently. Committed to continuous learning and regularly updating skills with the latest advancements in Synopsys tools and methodologies.

Overview

8
8
years of professional experience

Work History

Senior Engineer – PD STA

Cyient Ltd
07.2022 - Current
  • I have defined block-level floorplans, managed macro placement, and developed power plans, ensuring the floorplan remained clean and stable. I executed standard cell placement and routing (PnR) using ICC2, optimizing congestion and wire lengths for timing closure. I also implemented and optimized clock tree structures to minimize power consumption and noise. After routing, I managed to clean all violations and ensured the design was LVS clean.
  • In the area of DRC and LVS, I utilized Calibre and IC Validator, executing rule decks provided by various foundries such as TSMC, GF, Intel, and UMC. I played a key role in implementing PV flows at the block level by referencing previous scripts, serving as the point of contact for flow creation. Additionally, I executed flows to resolve antenna violations.
  • For power IR drop fixes, both static and dynamic, I employed techniques like defining keep-outs, swapping cells, and providing more power resources, guided by detailed reports from Redhawk. I generated SPEFs after merging the GDS from layout and used them for STA.
  • I performed Static Timing Analysis using Synopsys PrimeTime to meet timing constraints, conducting multi-corner multi-mode (MCMM) analysis to ensure timing closure across all PVT corners, and debugged and resolved setup, hold, and crosstalk violations. I developed and maintained TCL scripts to automate various physical design tasks, including the creation of PV and STA flows at the block level, and wrote scripts to efficiently resolve multiple DRVs by analyzing report endpoints.
  • My extensive hands-on experience with Synopsys tools like ICC2, PrimeTime, StarRC, IC Validator, and DC Compiler, combined with a commitment to continuously updating my skills with the latest advancements in tools and methodologies, has enabled me to enhance design productivity by creating custom scripts for design rule checking, report generation, and data analysis.

Physical Design Engineer VLSI

Risetime Semiconductors
04.2021 - 06.2022
  • Carried out Floorplan to Routing and performed iterations on ECO and fixes also the Timing fixes
  • Analysed the Reports and issues, worked on Block level STA implementing and Timing closure
  • Checked & Analysed the Design Rule Violations using ICV Tool.
  • PV drc fixes at my block level post updating the PV flow.

IT Full stack Java Developer

NTT DATA Formerly Dell Services
01.2017 - 03.2019


  • I worked on migrating an 16-year-old advanced cargo website for Lufthansa Airlines, where I utilized Java for coding and debugging issues using the Eclipse tool.
  • For database management, I employed SQL Server Management Studio, using SQL scripting to execute and filter data. My hands-on experience with ASP.NET and ADO.NET enabled me to develop effective strategies by integrating both Java and .NET for designing new features for the website.
  • Additionally, I worked as a data analyst for the CYC Health Cover project in the USA, where I supported the team in resolving tickets related to the application, including claims resolution.

Education

B.Tech (ECE) -

KITS(JNTU Kakinada)

Inter (10+2) - undefined

Board of Intermediate, Andhra Pradesh

10th - undefined

SSC

Physical Design Training - VLSI SEMICONDUCTORS

Sumedha IT VLSI Training Institute
Hyderabad
04.2001 -

Skills

  • Floorplan
  • Power Plan
  • IR Drop
  • Placement
  • DRCs
  • Congestion
  • Extraction
  • Static Timing Analysis (POST STA)
  • Clock Tree Synthesis (CTS)
  • Routing and Antenna Violation fixing
  • ECO Flow
  • Crosstalk and Noise Analysis
  • Chip level PV setup activities
  • Timing and DRV fixes using Prime time - DMSA
  • TCL scripting
  • LYNX flow
  • Make flow
  • Java,SQL

Leadership Experience

Volunteered and contributed as Host for cultural, technical, and social programs

Toolsused

  • Synopsys ICC2
  • Primetime
  • Redhawk
  • Fusion Compiler
  • DC compiler
  • Star RC
  • IC-Validator

Projects

Rise time Semiconductors, Hyderabad, 04/2021, 06/2022, Project 1, 16 nm, ~50k, 12, 800 MHz, ICC2, Star RC, Prime Time, Calibre, 3, Carried out Floorplan to Routing and performed iterations on ECO and fixes also the Timing fixes Analysed the Reports and issues, worked on Block level STA implementing and Timing closure. Checked & Analysed the Design Rule Violations using ICV Tool. Rise time Semiconductors, Hyderabad, 08/2021, 11/2021, Project 2, 5 nm, ~80k, 4, 800 MHz, ICC2, Star RC, Prime Time, Calibre, 3, Done Floorplan to Routing and performed iterations Analysed the Reports and issues, working on Block level STA implementing and Timing closure. Checked & Analysed the Design Rule Violations using ICV Tool. PV setup for both block and full chip Rise time Semiconductors, Hyderabad, 03/2022, 06/2022, Project 3, 5 nm, ~65k, 6, 800 MHz, ICC2, Star RC, Prime Time, Calibre, 4, Done Floorplan to Routing and performed iterations Worked on Block level STA implementing and Timing closure. Checked & Analysed the Design Rule Violations using ICV Tool PV setup for both block and full chip Block level IR drop setup & EM analysis and Fixes Cyient limited, Hyderabad, 07/2022, 11/2022, Project 4, 28 nm, 1M, 10, 1.1GHz, ICC2, Star RC, Prime Time, ICV, Redhawk, 2, Handled Floorplan to Routing Performed ECO iterations and fixes, and Timing fixes STA setup for both block and full chip Block level IR drop & EM analysis and Fixes, Antenna fixes PV drc fixes at my block level post updating the PV flow Cyient limited, Hyderabad, 07/2022, 11/2022, Project 4, 22 nm, 1M, 20, 1.6GHz, ICC2, Star RC, Prime Time, ICV, Redhawk, 2, Done Floorplan to Routing and solved ECO fixes, Ran Block level IR drop & EM analysis and Fixes, Section level owner . Block level IR drop & EM analysis and Fixes, Antenna fixes PV drc fixes at my block level post updating the PV flow Set STA flow for the blocks for to perform ECOs at block level Cyient limited, Hyderabad, 12/2022, 05/2023, Project 6, 32 nm, 1M, 40, 3.2GHz, ICC2, Star RC, Prime Time, ICV, Redhawk, 1, Done Floorplan to Routing and Performed PV for entire block Ran Block level IR drop & EM analysis and Fixes, Section level owner . Block level IR drop & EM analysis and Fixes, Antenna fixes Updated the STA flow and worked on ECOs. Cyient limited, Hyderabad, 06/2023, 11/2024, Project 7, 28 nm, 1M, 30, 3GHz, ICC2, Star RC, Prime Time, ICV, Redhawk, 1, Done Floorplan to Routing and Performed ECO Ran Block level IR drop & EM analysis and Fixes, Section level owner . Updated the STA flow and worked on ECOs and timing fixes Minimal analysis on block level IR Cyient limited, Hyderabad, 01/2024, 03/2024, Project 8, 16 nm, ~40k, 6, 3GHz, ICC2, Star RC, Prime Time, ICV, Redhawk, 1, Done Floorplan to Routing and Performed ECO Ran Block level IR drop & EM analysis and Fixes, Section level owner . Updated the STA flow and worked on ECOs and timing fixes Minimal analysis on block level IR Client AMD, 03/2024, Present, Project, 6 nm, 2.5M, 18, 1GHz, ICC2, Star RC, Prime Time, ICV, Redhawk, 1, Basic look after on synthesis where pushing for pre layout STA and Performing Post layout STA .Performing timing and cross talk analysis Resolving ECO fixes with DMSA . Interacting with the constraint team and PD team for block optimization where to analyze and debug and giving feedback to block PD team.

Scriptinglanguages

  • TCL Scripting
  • Java

Training

Sumedha IT VLSI, Hyderabad, Telangana, 04/2019, 09/2019, Trained on ASIC Design Flow, Physical Design

Interests

Playing cricket and represnted at Central zone at University level

Part of inter Corporate cricket team inside employer and played at different levels

Dancing and composing is a special skill that keeps me alive and be more effective and active even in my work

Timeline

Senior Engineer – PD STA

Cyient Ltd
07.2022 - Current

Physical Design Engineer VLSI

Risetime Semiconductors
04.2021 - 06.2022

IT Full stack Java Developer

NTT DATA Formerly Dell Services
01.2017 - 03.2019

Physical Design Training - VLSI SEMICONDUCTORS

Sumedha IT VLSI Training Institute
04.2001 -

B.Tech (ECE) -

KITS(JNTU Kakinada)

Inter (10+2) - undefined

Board of Intermediate, Andhra Pradesh

10th - undefined

SSC

Similar Profiles

CREATE PROFILE
THOUSIF SHAIKVLSI PHYSICAL DESIG ENGINEER