Capital Market Investing
Trivid Singh
VLSI Design
Bangalore
You only have to do a few things right in your life so long as you don’t do too many things wrong.
Warren Buffett
Summary
8+ years of a diversified yet fructifying experience in the chip design.
Problem solving roles catering to varied responsibilities within chip design
Close to 8 tape-outs comprising of varying responsibilities within RTL2GDSII Flow
Consistent believer in Automation for swifter TAT
Fluent handshaking capabilities within cross-domain/cross-regional teams
Desire to deep-dive into problems within semiconductor manufacturing and revenue forecasting for OEM considering the bigger perspective of overall business by expanding primary tech capabilities with the off-shore work in the investment arena identifying caveats in business model
Overview
10
10
years of professional experience
Work History
SoC Design Engineer
Intel Technology India Pvt. Ltd
Bengaluru
07.2022 - Current
- Working on Thermal sensor IP for overall IP implementation resulting into handshake with cross-domain teams. Trending with target completion within 2 months from start of execution i.e. 66% of identified timeline
- Worked on Intel Caliber flow for all partitions of DDR IP inclusive of waiver identification and eco estimation within 75% identified timeline
- Worked on timing flows to identify initial caveats in partition level runs for DDR IP.
Staff Physical Implementation Engineer
Samsung R&D Bangalore, SSIR
Bengaluru
12.2020 - 07.2022
- Well versed with cross-demographic/cross-domain/Cross-client/EDA-SOC interactions
- 3 tape-outs owning CPU wrapper partiton.
- Sole ownership on Methodology debugs for all partitions
- Automation /ScriptingDevelopment reducing productivity issues & timely execution
- 4nm/5nm process nodes in 3 tape-outs
- Owned CPU Wrapper Block
- Full ownership of Synthesis/STA inclusive of constraints generation & Sign-off
- VCLP/Spyglass/FEV debugs and verification
- FLAT STA involving hierarchical design related issues
- Understood & Executed Duty-Cycle distortion flow
Lead Product Engineer
Cadence Design Systems, CDNS
Noida
01.2018 - 11.2020
- Core-team member for Tempus ECO flows
- Performed within Flow Development for few Tier1 SOC Design Companies
- Established Manual ECO & GUI enhancements
- Core team member on Paradime and Multi-power domain flows
- Core-team member on Netlist pruning & Corner pruning for faster convergence.
Component Design Engineer
Intel Technology India Pvt. Ltd
Bengaluru
07.2014 - 12.2018
- 4 tape-outs
- 10 blocks with increasing utilization targets of 65%
- Dealt with Highest frequency target of 750Mhz
- Dealt with highest gates Count of 7M
- Dealt with highest Macro count of 700
- Performed RTL2GDSII Flow Activities
- Area Estimation and Initial Logic Optimization during Synthesis
- Automations based on various log debugs
- Place2Route Implementation
- STA/Intel Caliber closure for timing Signoff
- IR closure for power grid robustness
Intern
LSI R&D
Pune
07.2013 - 06.2014
- Digital Physical Design Implementation for Networking Chip (Technology: TSMC 16ff) Development Tools: IC Compiler (routing design), Primetime(STA analysis) Responsibility:
- Owned 2 small designs as part of Internship
- Block level implementation includes right from floorplanning to routing in ICC followed with STA analysis in PT, DRC/LVS analysis in calibre
- Full Design closure with DFT logic inserted.
Education
Bachelors of Engineering (Hons) - Electrical & Electronics
08.2009 - 06.2014
Master of Science - Mathematics
08.2009 - 06.2014
Skills
Qualitative problem solving
Design engineering
Product Development
Capital Market Investing
Angel Investing
Vocalist
Trained Vocalist
Interests
Product Management
Macroeconomics
Real Estate
Revenue Forecasting
Business Development
Capital Market Investing/Real Estate/Angel Investing/Macro Economics
Co-founded Stealth Mode Startup in 2020 dealing in capital investment of HNIs through various channels including capital market investment via portfolio assessment, Unsecured money lending via personal loans & derivative trading
Work Availability
monday
tuesday
wednesday
thursday
friday
saturday
sunday
morning
afternoon
evening
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Timeline
SoC Design Engineer - Intel Technology India Pvt. Ltd
07.2022 - Current
Staff Physical Implementation Engineer - Samsung R&D Bangalore, SSIR
12.2020 - 07.2022
Lead Product Engineer - Cadence Design Systems, CDNS
01.2018 - 11.2020
Component Design Engineer - Intel Technology India Pvt. Ltd
07.2014 - 12.2018
Intern - LSI R&D
07.2013 - 06.2014
Birla Institute of Technology And Science, Pilani - Bachelors of Engineering (Hons), Electrical & Electronics
08.2009 - 06.2014
Birla Institute of Technology And Science, Pilani - Master of Science, Mathematics
08.2009 - 06.2014