Summary
Overview
Work History
Education
Skills
Certification
Software
Languages
Timeline
Statement
WORKSHOP
Statement
Hi, I’m

Tushar Chauhan

Kashipur, Uttarakhand

Summary

An Electronic engineer with a technical background and a passion for innovation, looking for opportunity in the field of VLSI industry as Design, verification or Testing Engineer, skilled in analog and digital circuit design, verification, and testing. Holds Masters and bachelors degrees in VLSI, with expertise in digital ICs design and verification. Actively seeks opportunities to stay current with advancements in the electronics industry and utilize emerging technologies to solve complex engineering challenges. Committed to continuous learning and problem-solving, able to adapt to evolving project requirements and deliver innovative solutions. Eager to contribute skills and expertise for professional growth in engineering.

Overview

5
years of professional experience
1
Certificate

Work History

Contemporary Verification Consultants(CVC) Pvt Ltd

DVE TRAINEE
07.2022 - 09.2024

Job overview

  • Worked on projects related to: Verilog, System Verilog, UVM, Test case development, verify Assertions.
  • S2P (Serial to Parallel ) Interface: Verified using System Verilog UVM
  • ALU Verification IP: Verification of ALU IP using System Verilog Layered Testbench.
  • Tools used: Mentor Graphics, Pylinter

Vishwanath Paper and Boards

Instrumentation Technician Trainee
01.2022 - 06.2022

Job overview

  • Role: maintaining Pneumatic and Hydraulic automation in the plan checking functionality of Micro-controllers used in the plant.
  • Removed damaged instruments and repaired components.
  • Monitored supply levels and requested additional spare parts, manuals, or tools.

Truechip Solutions

Intern
05.2019 - 06.2019

Job overview

  • Design and verification of digital RTL designs using Verilog language in Xilinx Software.
  • Project: Design and Verification of 4-bit Vedic Multiplier.
  • Language- Verilog, Software- Xilinx ISE design Suite 14.2

Education

Karunya Institute of Technology And Sciences
Coimbatore, India

M.Tech from VLSI
06-2026

University Overview

  • 7.83 CGPA
  • SPI Protocol: Verification of Serial Peripheral Interface protocol using System verilog layered testbench. Language- system Verilog, Software- Cadence Xcelium.
  • Quantum Circuit Security: Secured Quantum Circuits using Random Reversible gate technique. Language- Python, SDK- IBM Qiskit.
  • Low Power Dynamic Comparator: 80% reduction in power compare to existing design, software-Cadence Virtuoso, Technology-180nm CMOS.
  • APB Protocol: Implementation and verification of APB Protocol using System Verilog Testbench. Language: Verilog and System Verilog, Software: Xilinx Vivado

Chandigarh University
Mohali, India

Bachelor of Engineering from ECE
06.2021

University Overview

  • 6.56 CGPA
  • Project: "Stock Analyzer": Creating and maintaining stock analyzer software-based project for analyzing and predicting the future stock values of different organizations using Machine Learning Algorithm, Software used: JupyterNotebook, Language: Python

Skills

FPGA emulation Functional Verification Verilog System Verilog Python UVM C OOPS Linux Digital Electronics Analog Electronics Testing Protocols

Certification

  • Introduction to Linux, LinkedIn Learning.
  • System Verilog Basics - RTL Constructs, Udemy (Srinivasan Venkatramanan).
  • System Verilog Interface Get Set Go, Udemy (Srinivasan Venkatramanan).

Software

Cadence Virtuoso Cadence Xcelium Xilinx Vivado Xilinx ISE design suite 142 STM32 Synopsys EDA VS code

Languages

English | Hindi

Timeline

DVE TRAINEE
Contemporary Verification Consultants(CVC) Pvt Ltd
07.2022 - 09.2024
Instrumentation Technician Trainee
Vishwanath Paper and Boards
01.2022 - 06.2022
Intern
Truechip Solutions
05.2019 - 06.2019
Karunya Institute of Technology And Sciences
M.Tech from VLSI
Chandigarh University
Bachelor of Engineering from ECE

Statement

Statement

Above information is correct, verified and given by me.

Tushar Chauhan

(Open to Work)

WORKSHOP

WORKSHOP
  • Three-day Workshop on ASIC design using Synopsys EDA tool at VIT Vellore.
  • Hands-on Training session - "Empowering the Future: Digital Logic implementation with FPGA kits- India Semiconductor mission" at Karunya university in association with Corel Technologies.
  • "A way to Semiconductor Industry" at Karunya University in association with SiMa.ai India Pvt Ltd.

Statement

Statement

Above information is correct, verified and given by me. 

Tushar Chauhan (Open to Work)

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