TWINKLE BHARDWAJ

I am a skilled Verification Engineer with a strong background in Soc level verification and digital VLSI design. With extensive experience in communication IPs and effective collaboration with cross-functional teams, I have excelled in developing rigorous test cases and debugging critical issues. My academic achievements and recognition in high impact projects showcase my commitment to delivering innovative solutions and enhancing semiconductor performance

• Best Paper Award, MASCON 2021 - IEEE Conference
• Research Paper, Power consumption and delay comparison of modified topologically compressed flip-flop
• Silver Medal, Silver Medalist - NIT Delhi
• Excellence in Debugging, Received award for high-impact bug identification during late regression phase of K342 project

S32K5 MCU Family - Verification of communication IPs for the S32K5 MCU Family. Developed and executed SoC-level test plan for communication peripherals including DSPI, LPUART, SAI, and FLEXIO. Created SV and C-based directed and random test cases to validate complex SoC integrations. Performed functional and toggle coverage closure and collaborated with RTL and firmware teams on bug triage.

S32S125 MCU Family – Timer & Communication IP Verification. Led verification efforts for peripherals including FLEXRAY, PIT, TRIGMUX, and DSPI. Implemented feature-specific testbenches and analyzed coverage gaps to optimize test effectiveness. Owned full traceability and ensured coverage signoff in coordination with multi-site stakeholders.

S32K342 MCU – Contributed to silicon readiness by validating corner cases and running complete regression cycles. Identified critical issue in new clock mode request, enabling a successful final tape-out. Recognized by management with award for exceptional debug and problem-solving efficiency.