Summary
Overview
Work History
Education
Skills
Languages
Personal Information
Accomplishments
Timeline
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Uma B S

Bangalore

Summary

Accomplished Digital Design Engineer with extensive experience at Intel Technology, specializing in backend flow methodology and optimization. Proven track record in enhancing PPA targets and resolving complex timing issues. Proficient in TCL and Perl, demonstrating strong analytical skills and a commitment to quality in high-stakes environments.

Overview

7
7
years of professional experience

Work History

DIGITAL DESIGN ENGINEER

Intel Technology
Bengaluru
08.2022 - 07.2023
  • Worked in developing utilities in TCL/perl for design methodology and flow development to drive faster execution.
  • Worked in Synopsys Fusion Compiler DP flow enhancements by developing and evaluating healthchecks stagewise.
  • Led IP integration in 5nm node and developed utilities to enable to quality and reliability.
  • Implemented optimized floorplan and power distribution networks for reliable power, area and performance (PPA) targets.
  • Worked closely with RTL team to resolve timing issues.
  • Worked in EMIR checks and identify and resolve issues.
  • Contributed to LV (ICV) checks and resolved metal DRC and base DRC.

PRINCIPAL ENGINEER DESIGN ENGINEERING

GlobalFoundries
Bengaluru
07.2021 - 07.2022
  • Handled chip level PnR execution including IO planning, Bump assignment, RDL routing, floorplan and clock tree building using cadence Innovus tool.
  • Worked on CTS mesh building for complex test chips with controlled latency and skew for timing convergence.
  • Working on PPA benchmarking for customer requirements.

Sr. ENGINEER DESIGN ENABLEMENT

GlobalFoundries
Bengaluru
12.2019 - 06.2021
  • Performance benchmarking using GF's different libraries to meet the demanding requirements of power, performance and area and following the value chain from the end customer using Cadence Innovus/Synopsys ICC2.
  • Standard cell QA analysis for subset of internal built libraries and provide feedback on layout and performance quality.
  • Handled top level PnR execution of the testchips, fixing design floorplan issues, fixing signoff timing (PrimeTime) and DRV rules using synopsys ICC2/PrimeTime tools.
  • Enablement of flows for SLM IP's execution and integration.

GRAPHICS HARDWARE ENGINEER

Intel Technology
Bengaluru
04.2017 - 04.2019
  • Converged multiple blocks of latest gen-graphics core with multi-million gates count from RTL to GDSII as 'Partition Execution Owner (PEO)' of 14nm and 10nm Technology nodes using Lynx Design Manager, Synopsys Design Compiler and Synopsys ICC/ICC2 tools.
  • Good Knowledge in physical design domains mainly in floorplanning, placement, clock tree synthesis, routing, ECO implementation through STA, physical verification (LVS/DRC fixes), reliability verification (IR drop analysis, Electromigration), LEC checks for functionality.
  • Worked on Crosstalk and signal integrity issues.
  • Worked on manual Engineering Change Order (ECO) for timing and functionality convergence using Lynx Design Manager and Synopsys Primetime tool.

INTERN

Qscos
Bengaluru
10.2016 - 03.2019
  • Worked on 45nm TSMC 250MHz block. Performed RTL to GDSII convergence with respect to power, performance and area (PPA) aspects using Cadence Innovus tool.
  • Handled and fixed timing, DRV violations. Achieved routable dB with minimal shorts and DRC's.

Education

MTech - VLSI Design and Embedded Systems

JSSATE (JSS Academy of Technical Education)
Bengaluru
05.2016

B.E - Electronics and Communication

RNSIT (RNS Institute of Technology)
Bengaluru
05.2014

Diploma - Electronics and Communication

P.V.P Polytechnic
Bengaluru
05.2011

Skills

  • Backend Flow Methodology
  • Floorplanning
  • Placement
  • Optimization
  • CTS build debug
  • PostRoute SI fix
  • STA closure
  • DC
  • ICC2
  • PrimeTime
  • StarRC
  • Innovus
  • Tempus
  • PVS
  • Voltus
  • UNIX
  • Perl
  • Tcl
  • Verilog

Languages

  • Kannada
  • English
  • Hindi

Personal Information

  • Father's Name: Shankarappa
  • Date of Birth: 03/08/93
  • Nationality: Indian

Accomplishments

  • Received the Excellence Award for successfully achieving Power, Performance, and Area (PPA) targets for designated technology libraries by utilizing optimized test cases and methodologies
  • Honored with Spotlight award for the seamless execution of chip-level integration and delivering on key Quality of Results (QOR) metrics, ensuring a robust and high-performance silicon design

Timeline

DIGITAL DESIGN ENGINEER

Intel Technology
08.2022 - 07.2023

PRINCIPAL ENGINEER DESIGN ENGINEERING

GlobalFoundries
07.2021 - 07.2022

Sr. ENGINEER DESIGN ENABLEMENT

GlobalFoundries
12.2019 - 06.2021

GRAPHICS HARDWARE ENGINEER

Intel Technology
04.2017 - 04.2019

INTERN

Qscos
10.2016 - 03.2019

MTech - VLSI Design and Embedded Systems

JSSATE (JSS Academy of Technical Education)

B.E - Electronics and Communication

RNSIT (RNS Institute of Technology)

Diploma - Electronics and Communication

P.V.P Polytechnic

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Uma B S