Summary
Education
Skills
Websites
Accomplishments
Projects
Positions Of Responsibility
Timeline
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Unnati Bhatnagar

Summary

Motivated and detail-oriented final-year B.Tech Electronics and Communication Engineering student with a strong academic background and hands-on experience in circuit design, VLSI, and digital electronics. Proficient in EDA tools such as LTspice, and basic HDL programming with Verilog. Demonstrates strong analytical and problem-solving skills through academic projects in low-power digital design and analog circuit simulation. Effective team player with leadership experience in technical and marketing roles. Seeking to contribute to innovative engineering solutions in a core electronics role.

Education

B.Tech - Electronics and Communication Engineering

Indira Gandhi Delhi Technical University For Women
Delhi
05-2026

Senior Secondary (XII) - CBSE

Adarsh Jain Dharmik Shiksha Sadan
Najafgarh, New Delhi
01-2022

Secondary (X) - CBSE

Tagore Senior Secondary School
Mayapuri, New Delhi
01-2020

Skills

  • C
  • C
  • Verilog
  • Python
  • LTspice
  • Xilinx Vivado
  • CMOS Circuit Design
  • Digital Electronics
  • Microprocessors
  • VLSI Design
  • Data structures and algorithms
  • HTML
  • CSS
  • JavaScript
  • Bootstrap
  • MySQL
  • OOPs
  • DBMS

Accomplishments

  • Zonal Level Achiever – Debate and Declamation Competitions
  • Zonal Level Achiever – Science Seminar Competition

Projects

  • Research paper on Transconductance Enhancement Techniques in CMOS Amplifiers (Ongoing)
    Conducting research on low-power transconductance enhancement methods for analog CMOS amplifiers. Exploring circuit-level techniques such as current reuse, positive feedback, and gain boosting to improve amplifier performance and energy efficiency. Performing simulation-based validation using LTspice tool. Targeting future publication in an academic journal or conference.
  • Synchronous FIFO Project: Designed and implemented a Synchronous FIFO (First-In-First-Out) memory buffer where both read and write operations are controlled by the same clock domain using Verilog technology.
  • Single Port RAM: Designed and implemented a Single Port RAM module for storing and retrieving data with one access port shared for both read and write operations using Verilog technology.
  • Food Delivery Frontend Website: Created a responsive food delivery UI using HTML, CSS, and Bootstrap, Improved design and navigation, enhancing user experience

Positions Of Responsibility

  • Head Coordinator – Robotics Team, Innerve (Tech Fest), Managed cross-functional tasks and documentation for competition
  • Marketing Coordinator – E-Cell, Conducted outreach and engagement campaigns for student entrepreneurship events, Collaborated with design and content teams for event promotion

Timeline

B.Tech - Electronics and Communication Engineering

Indira Gandhi Delhi Technical University For Women

Senior Secondary (XII) - CBSE

Adarsh Jain Dharmik Shiksha Sadan

Secondary (X) - CBSE

Tagore Senior Secondary School
Unnati Bhatnagar