Verification Engineer with 1 year of experience at Micron, specializing in LPDDR5 memory array level verification using UVM methodology. Proficient in SystemVerilog, functional coverage, and assertion-based verification. Master's graduate in Embedded Systems from BITS Pilani, Hyderabad Campus, with a strong foundation in digital design, VLSI, and HDL programming, with a strong background in digital logic design, hardware verification, and simulation. Skilled in utilizing verification methodologies and tools, ensuring reliable and high-quality outcomes. Known for effective collaboration within cross-functional teams and adaptability to project changes. Valued for problem-solving abilities, attention to detail, and commitment to achieving results.
· Implemented Rock, Paper, Scissors Game on Xilinx Zynq FPGA using Verilog HDL with 7 push-button input interfaces and VIO output display.
· Designed and simulated a single-cycle RISC-V processor supporting R-type, I-type, B-type, J-type, lw/sw instructions with Verilog HDL.