URVISH JANI
Hyderabad
Summary
Verification Engineer with 1 year of experience at Micron, specializing in LPDDR5 memory array level verification using UVM methodology. Proficient in SystemVerilog, functional coverage, and assertion-based verification. Master's graduate in Embedded Systems from BITS Pilani, Hyderabad Campus, with a strong foundation in digital design, VLSI, and HDL programming, with a strong background in digital logic design, hardware verification, and simulation. Skilled in utilizing verification methodologies and tools, ensuring reliable and high-quality outcomes. Known for effective collaboration within cross-functional teams and adaptability to project changes. Valued for problem-solving abilities, attention to detail, and commitment to achieving results.
Overview
1
1
year of professional experience
1
1
Certification
Work History
LPDDR5 Verification Engineer
Micron Technology
07.2024 - 05.2025
- Detected major flaws in the legacy scoreboard that the DGC (China team) developed in 2011. Updated it with precise checks and tested it rigorously by intentionally rewiring the netlist. The revised scoreboard caught failures missed previously and achieved a 100% pass rate with the correct netlist in a Tapeout set.
- Owned full responsibility for coverage closure; added over 6.5 million new bins, bringing the total to 11,818,777 bins—the highest in the team's history. Achieved 100% functional coverage for the first time in the TB team by developing six new directed test cases targeting array-level signals.
- Updated multiple directed and random test cases to accommodate architectural changes in the DRAM array from the previous project.
- Provided support to multiple business unit verification teams in setting up their testbenches and scoreboards, enhancing reusability and consistency.
- Mentored two interns (joined January 2025), guiding them through DRAM fundamentals and testbench-specific concepts.
- Internship: Jan 2024 – Jul 2024
Education
M.E. - Embedded Systems
BITS Pilani
01.2024
B.E. - Electronics
M.S. University
01.2021
H.S.C - undefined
Shree Narayan Vidyalaya
01.2017
S.S.C - undefined
Sardar Vallabhbhai Vidyalaya
01.2015
Skills
- Languages & HDLs: SystemVerilog, Verilog, Python, TCL
- Verification: UVM, Functional Coverage, Assertion-based Verification
- Tools: Cadence Virtuoso, Cadence Simvision, Git
- Protocols: LPDDR5
- Platforms: Xilinx FPGA, Linux
- Scripting languages proficiency
- Hardware description languages
- Testbench development
- Gate-level simulations
- Timing analysis
- UVM methodology
- Constraint random verification
- Functional coverage
- Assertion-based verification
- Verification planning
- Teamwork
Academic Projects
· Implemented Rock, Paper, Scissors Game on Xilinx Zynq FPGA using Verilog HDL with 7 push-button input interfaces and VIO output display.
· Designed and simulated a single-cycle RISC-V processor supporting R-type, I-type, B-type, J-type, lw/sw instructions with Verilog HDL.
Certification
- Python Programming – NPTEL, IIT Madras
- Verilog HDL: VLSI Hardware Design Comprehensive Masterclass – Udemy
Timeline
LPDDR5 Verification Engineer
Micron Technology
07.2024 - 05.2025
B.E. - Electronics
M.S. University
H.S.C - undefined
Shree Narayan Vidyalaya
S.S.C - undefined
Sardar Vallabhbhai Vidyalaya
M.E. - Embedded Systems
BITS Pilani
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