V. SONIYA

Recent graduate with a master’s degree in VLSI Design, equipped with strong knowledge in RTL-to-GDSII flow, physical verification, and sign-off stages. Demonstrates a keen ability to apply theoretical concepts in practical scenarios, contributing effectively to team objectives within the semiconductor industry. Eager to leverage academic expertise in a Physical Design Engineering role while advancing professional skills.

• Static Timing Analysis, UDEMY
• Linux for Beginners: Linux Basics, UDEMY

1. ORCA_top.

Technology : 32nm, No.of macro: 40, Layer : 9, Std.cell count : 56013, No.of clock : 7, Frequency : 416MHz, Responsibilities include iterative Floor plan, IO ports placement, Power planning, Placement and CTS reviews, Routing and DRC checks. 

2. Design and Evaluation of Two Phase Adiabatic Dynamic Logic for Low Power Applications.

Aim: To design adiabatic principles and innovative clocking techniques to achieve enhanced power efficiency and performance in electronic system.

• Physical design course, TAKSHILA ACADEMY
• VLSI Design Methodologies certified from MAVEN SILICON, Bangalore

• Telugu
• Hindi
• English

• Awarded Merit Scholarship under Prime Minister's Scholarship Scheme
• Certificate issued by NMDC Bacheli for Brilliant student Award

 Cooking, Travelling, Learning New Things, Yoga, Hard working, Quick learn