Vagesh Revankar
Bangalore
Summary
Electronics and Communication Engineer with expertise in Analog & Mixed-Signal Layout Design, SKILL scripting automation, and IC physical verification. Experienced in TSMC28, TI28, and CO21 (65nm TI technology) for high-performance ADCs, power management, and clocking circuits. Skilled in LVS, DRC, ANT verification (Assura & PVS) and layout automation using SKILL programming, demonstrating strong technical and problem-solving abilities.
Overview
2
2
years of professional experience
Work History
Layout Engineer
Texas Instruments India Ltd
Bangalore
07.2023 - Current
- Designed layouts for ADCs, phase interpolators, clocks, MUXs, GPIOs, LDOs, frequency and phase dividers, bandgap references, bias circuits, comparators, and power management blocks.
- Worked on TSMC28, TI28, and CO21 (65 nm) nodes, optimizing area and performance.
- Performed LVS, DRC, and ANT verification (Assura and PVS) and ensured design compliance.
- Developed SKILL scripts for layout automation, reducing manual effort, and improving efficiency.
- Implemented circuit parasitic extraction and reduction, and latch-up mitigation strategies to enhance reliability.
Layout Engineering Intern
Texas Instruments India Ltd
Bangalore
01.2023 - 07.2023
- Assisted in analog layout design and physical verification for mixed-signal ICs
Education
B.E. - Electronics & Communication, Technological Innovations for Social Transformation
KLE Technological University
Hubballi04-2023
Skills
- Analog Layout Design: Cadence Virtuoso, PVS, Assura
- Physical Verification: LVS, DRC, ANT
- Semiconductor & IC Fabrication: CMOS, IC design rules, matching techniques
- Automation & Scripting: SKILL programming for layout automation
- Technology Nodes: TSMC28, TI28, CO21 (65nm)
- Reliability Techniques: ESD, latch-up mitigation, parasitic extraction
- Soft Skills: Problem-solving, teamwork, communication
Projects
- SKILL Scripting for Layout Automation - Created scripts to enhance efficiency like automated Quantus parasitic extraction process.
- High-Precision ADC Layout, Optimized matching techniques and parasitic reduction.
- Ethernet PHY Team Contribution - Worked on high-speed data transmission circuits for TI's Ethernet transceivers.
- Designed layouts for Bandgap Reference, LDOs, Comparators, Power Management Blocks.
Personal Information
Title: Analog Layout Engineer
Timeline
Layout Engineer
Texas Instruments India Ltd
07.2023 - Current
Layout Engineering Intern
Texas Instruments India Ltd
01.2023 - 07.2023
B.E. - Electronics & Communication, Technological Innovations for Social Transformation
KLE Technological University
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