Vaibhav Malani

• Activities involved PLL locking bringup in test mode / Frequency plan & exceptions generation creation for over 1000 domains
• Cross corner header generation / Timing simulation debugs / SDC issues causing low coverage / configuring multiple Clock instruments using IJTAG (ICL/PDL)

• Part of flow development for Shelling/Run time reduction methodology
• Contributed to flow development for ICL verification for early identification of ICL/Design mismatch
• Multiple other utility development's based on ticket's raised

• Pre-Scan RTL DRC checks , RTL scan structures insertion & DRC check's, CLP & FV cleanup
• Synth DRC checks for scan inserted netlist on DC & FC tools / wrapper reviews / compression metrics / test point insertion analysis & multiple other signoff metrics
• Core level ATPG coverage analysis / chain tracing across various modes & other ATPG signoff metrics
• Sync up with Synth,PD & DFT STA team for timing constraints / placement requirements / pipeline ECO's etc

• Achieve targets across various milestones like P1/P2/P3/PD/BTO/MTO for coverage / simulations / pattern generation & delivery.
• Post silicon debug support
• Acquired good knowledge of DFT architecture & tools

Started in ATPG bubble with post silicon diagnosis for fallout/margin issues & contributed in development of in-house tool ( QHOT ) for diagnosis.