Vaishali Mandadi

Responsibilities:
• Monitor network capacity and performance to diagnose and resolve complex network problems.
• Provided complete end-to-end engineering and installation of route-based IP network solutions
• Verified and validated switch configurations to ensure compliance with network design and security standards.
• Conducted thorough reviews of VLAN, trunking, port security, and spanning tree configurations to ensure optimal network segmentation and loop prevention.
• Documented validation procedures, results, and any deviations from expected performance, providing detailed reports
• Diagnosed and resolved issues identified during the validation process, working closely with other network engineers and vendors as needed.
• Implemented corrective actions and re-tested configurations to confirm resolution of identified problems.
• Inspected and reviewed device configurations to ensure consistent duplex settings across connected devices (e.g., full-duplex or half-duplex) and avoid mismatches.
• Managed and documented daily project-related changes using ServiceNow, ensuring accurate tracking and seamless integration into the existing system.
• Coordinated and implemented new project-related changes, aligning them with overall project goals and timelines.
• Cisco routers and switches upgrades as per the project requirement
• Redundancy Testing for Tenant and BMN network - Conducted failure simulations to verify automatic traffic rerouting and system resilience and Tested backup systems and failover mechanisms to ensure seamless operation during outages.
• Collaborated with NSPs during the planning and deployment of new network services and infrastructure upgrades , Ensured alignment of NSP capabilities with organizational requirements during network expansions and changes. Provided technical guidance and support to NSPs during the troubleshooting and resolution of complex network issues.
• Configured PDU ports to integrate seamlessly with the broader network and data center infrastructure, supporting critical services and operations.
• Diagnosed and resolved issues related to PDU port configurations, including connectivity problems and power distribution faults.

• Enforced Automation in software to perform various tasks using Tcl scripts to improve efficiency, integrity, and overall productivity
• Created functional models using Verilog and simulated to verify the behavior of digital systems
• Undertook Cadence Virtuoso Schematic/Layout XL for IC design and layout -Hence utilizing and improving my understanding of semiconductor design rules and physics.
• Optimized layout designs to meet area targets for 22nm and 45nm technology nodes of various memory components
• Thoroughly resolved design rule errors individually, ensuring a clean DRC (Design Rule Checking) verification
• Performed LVS (Layout vs. Schematic) verifications to ensure compliance with design specifications and achievement of timing goals
• Aided layout design and development of a memory test chip using 22nm process technology, - analysis of critical paths, timing constraints, and interconnect parasitics - optimized the access time and overall performance of the test chip
• Enabled Automation for generation of scripts for Tessent FastScan ATPG facilitating the efficient creation of test patterns
• Authored a comprehensive Spec file for a chip design enabling simultaneous testing of 8 SRAMs and 4 Register Files
• Development and verification of Memory Views (Front-end views - liberty, tetramax, fastscan, verilog, mbist)
• Makefile Development and Management
• Gained exposure to functionality of SRAM, DFT, SCAN, Memory BIST, and ATPG design flows